From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [Qemu-devel] [PATCH v2 07/24] target-sparc: Introduce get_asi
Date: Tue, 23 Feb 2016 13:11:43 -0800 [thread overview]
Message-ID: <1456261920-29900-8-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1456261920-29900-1-git-send-email-rth@twiddle.net>
Replace gen_get_asi, and use it for both 32-bit and 64-bit.
For v8, do supervisor and immediate checks here.
Also, move save_state and TB ending into the respective
subroutines, out of disas_sparc_insn.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 508 +++++++++++++++++++++++++----------------------
1 file changed, 273 insertions(+), 235 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 7de5777..c9ec885 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1964,97 +1964,161 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
/* asi moves */
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
-static TCGv_i32 gen_get_asi(DisasContext *dc, int insn)
-{
+typedef enum {
+ GET_ASI_HELPER,
+ GET_ASI_EXCP,
+} ASIType;
+
+typedef struct {
+ ASIType type;
int asi;
+} DisasASI;
+static DisasASI get_asi(DisasContext *dc, int insn)
+{
+ int asi = GET_FIELD(insn, 19, 26);
+ ASIType type = GET_ASI_HELPER;
+
+#ifndef TARGET_SPARC64
+ /* Before v9, all asis are immediate and privileged. */
if (IS_IMM) {
-#ifdef TARGET_SPARC64
- asi = dc->asi;
-#else
gen_exception(dc, TT_ILL_INSN);
- asi = 0;
-#endif
+ type = GET_ASI_EXCP;
+ } else if (supervisor(dc)
+ /* Note that LEON accepts ASI_USERDATA in user mode, for
+ use with CASA. Also note that previous versions of
+ QEMU allowed ASI_P for LEON, which is incorrect. */
+ || (asi == 0xa
+ && (dc->def->features & CPU_FEATURE_CASA))) {
} else {
- asi = GET_FIELD(insn, 19, 26);
+ gen_exception(dc, TT_PRIV_INSN);
+ type = GET_ASI_EXCP;
+ }
+#else
+ if (IS_IMM) {
+ asi = dc->asi;
}
- return tcg_const_i32(asi);
+#endif
+
+ return (DisasASI){ type, asi };
}
static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
int insn, int size, int sign)
{
- TCGv_i32 r_asi, r_size, r_sign;
+ DisasASI da = get_asi(dc, insn);
+
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(size);
+ TCGv_i32 r_sign = tcg_const_i32(sign);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(size);
- r_sign = tcg_const_i32(sign);
+ save_state(dc);
#ifdef TARGET_SPARC64
- gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
+ gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
#else
- {
- TCGv_i64 t64 = tcg_temp_new_i64();
- gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
- tcg_gen_trunc_i64_tl(dst, t64);
- tcg_temp_free_i64(t64);
- }
+ {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
+ tcg_gen_trunc_i64_tl(dst, t64);
+ tcg_temp_free_i64(t64);
+ }
#endif
- tcg_temp_free_i32(r_sign);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
+ tcg_temp_free_i32(r_sign);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ }
+ break;
+ }
}
static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
int insn, int size)
{
- TCGv_i32 r_asi, r_size;
+ DisasASI da = get_asi(dc, insn);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(size);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(size);
+
+ save_state(dc);
#ifdef TARGET_SPARC64
- gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
+ gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
#else
- {
- TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t64, src);
- gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
- tcg_temp_free_i64(t64);
- }
+ {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t64, src);
+ gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
+ tcg_temp_free_i64(t64);
+ }
#endif
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+
+ /* A write to a TLB register may alter page maps. End the TB. */
+ dc->npc = DYNAMIC_PC;
+ }
+ break;
+ }
}
static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
TCGv addr, int insn)
{
- TCGv_i32 r_asi, r_size, r_sign;
- TCGv_i64 s64, t64 = tcg_temp_new_i64();
+ DisasASI da = get_asi(dc, insn);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(4);
- r_sign = tcg_const_i32(0);
- gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
- tcg_temp_free_i32(r_sign);
-
- s64 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(s64, src);
- gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
- tcg_temp_free_i64(s64);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
-
- tcg_gen_trunc_i64_tl(dst, t64);
- tcg_temp_free_i64(t64);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(4);
+ TCGv_i32 r_sign = tcg_const_i32(0);
+ TCGv_i64 s64, t64;
+
+ save_state(dc);
+ t64 = tcg_temp_new_i64();
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
+ tcg_temp_free_i32(r_sign);
+
+ s64 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(s64, src);
+ gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
+ tcg_temp_free_i64(s64);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+
+ tcg_gen_trunc_i64_tl(dst, t64);
+ tcg_temp_free_i64(t64);
+ }
+ break;
+ }
}
static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
int insn, int rd)
{
- TCGv val1 = gen_load_gpr(dc, rd);
- TCGv dst = gen_dest_gpr(dc, rd);
- TCGv_i32 r_asi = gen_get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn);
+ TCGv val1, dst;
+ TCGv_i32 r_asi;
+
+ if (da.type == GET_ASI_EXCP) {
+ return;
+ }
+ save_state(dc);
+ val1 = gen_load_gpr(dc, rd);
+ dst = gen_dest_gpr(dc, rd);
+ r_asi = tcg_const_i32(da.asi);
gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
gen_store_gpr(dc, rd, dst);
@@ -2062,23 +2126,34 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
{
- TCGv_i32 r_asi, r_size, r_sign;
- TCGv_i64 s64, d64 = tcg_temp_new_i64();
-
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(1);
- r_sign = tcg_const_i32(0);
- gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_size, r_sign);
- tcg_temp_free_i32(r_sign);
+ DisasASI da = get_asi(dc, insn);
- s64 = tcg_const_i64(0xff);
- gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
- tcg_temp_free_i64(s64);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
-
- tcg_gen_trunc_i64_tl(dst, d64);
- tcg_temp_free_i64(d64);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(1);
+ TCGv_i32 r_sign = tcg_const_i32(0);
+ TCGv_i64 s64, t64;
+
+ save_state(dc);
+ t64 = tcg_temp_new_i64();
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
+ tcg_temp_free_i32(r_sign);
+
+ s64 = tcg_const_i64(0xff);
+ gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
+ tcg_temp_free_i64(s64);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+
+ tcg_gen_trunc_i64_tl(dst, t64);
+ tcg_temp_free_i64(t64);
+ }
+ break;
+ }
}
#endif
@@ -2086,66 +2161,115 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
static void gen_ldf_asi(DisasContext *dc, TCGv addr,
int insn, int size, int rd)
{
- TCGv_i32 r_asi, r_size, r_rd;
+ DisasASI da = get_asi(dc, insn);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(size);
- r_rd = tcg_const_i32(rd);
- gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
- tcg_temp_free_i32(r_rd);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(size);
+ TCGv_i32 r_rd = tcg_const_i32(rd);
+
+ save_state(dc);
+ gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
+ tcg_temp_free_i32(r_rd);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ }
+ break;
+ }
}
static void gen_stf_asi(DisasContext *dc, TCGv addr,
int insn, int size, int rd)
{
- TCGv_i32 r_asi, r_size, r_rd;
+ DisasASI da = get_asi(dc, insn);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(size);
- r_rd = tcg_const_i32(rd);
- gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
- tcg_temp_free_i32(r_rd);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(size);
+ TCGv_i32 r_rd = tcg_const_i32(rd);
+
+ save_state(dc);
+ gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
+ tcg_temp_free_i32(r_rd);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ }
+ break;
+ }
}
static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- TCGv_i32 r_asi, r_rd;
+ DisasASI da = get_asi(dc, insn);
- r_asi = gen_get_asi(dc, insn);
- r_rd = tcg_const_i32(rd);
- gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
- tcg_temp_free_i32(r_rd);
- tcg_temp_free_i32(r_asi);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_rd = tcg_const_i32(rd);
+
+ save_state(dc);
+ gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
+ tcg_temp_free_i32(r_rd);
+ tcg_temp_free_i32(r_asi);
+ }
+ break;
+ }
}
static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- TCGv_i32 r_asi, r_size;
+ DisasASI da = get_asi(dc, insn);
TCGv lo = gen_load_gpr(dc, rd + 1);
- TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat_tl_i64(t64, lo, hi);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(8);
- gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
- tcg_temp_free_i64(t64);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(8);
+ TCGv_i64 t64;
+
+ save_state(dc);
+
+ t64 = tcg_temp_new_i64();
+ tcg_gen_concat_tl_i64(t64, lo, hi);
+ gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ tcg_temp_free_i64(t64);
+ }
+ break;
+ }
}
static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
int insn, int rd)
{
+ DisasASI da = get_asi(dc, insn);
TCGv val1 = gen_load_gpr(dc, rd);
TCGv dst = gen_dest_gpr(dc, rd);
- TCGv_i32 r_asi = gen_get_asi(dc, insn);
+ TCGv_i32 r_asi;
+ if (da.type == GET_ASI_EXCP) {
+ return;
+ }
+
+ save_state(dc);
+ r_asi = tcg_const_i32(da.asi);
gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
tcg_temp_free_i32(r_asi);
gen_store_gpr(dc, rd, dst);
@@ -2155,46 +2279,61 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- TCGv_i32 r_asi, r_size, r_sign;
- TCGv t;
- TCGv_i64 t64;
-
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(8);
- r_sign = tcg_const_i32(0);
- t64 = tcg_temp_new_i64();
- gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
- tcg_temp_free_i32(r_sign);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
+ DisasASI da = get_asi(dc, insn);
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ TCGv lo;
- /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
- whereby "rd + 1" elicits "error: array subscript is above array".
- Since we have already asserted that rd is even, the semantics
- are unchanged. */
- t = gen_dest_gpr(dc, rd | 1);
- tcg_gen_trunc_i64_tl(t, t64);
- gen_store_gpr(dc, rd | 1, t);
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ tcg_temp_free_i64(t64);
+ return;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(8);
+ TCGv_i32 r_sign = tcg_const_i32(0);
+
+ save_state(dc);
+ gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
+ tcg_temp_free_i32(r_sign);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ }
+ break;
+ }
- tcg_gen_shri_i64(t64, t64, 32);
- tcg_gen_trunc_i64_tl(hi, t64);
+ lo = gen_dest_gpr(dc, rd + 1);
+ tcg_gen_extr_i64_i32(lo, hi, t64);
tcg_temp_free_i64(t64);
+ gen_store_gpr(dc, rd + 1, lo);
gen_store_gpr(dc, rd, hi);
}
static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- TCGv_i32 r_asi, r_size;
+ DisasASI da = get_asi(dc, insn);
TCGv lo = gen_load_gpr(dc, rd + 1);
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t64, lo, hi);
- r_asi = gen_get_asi(dc, insn);
- r_size = tcg_const_i32(8);
- gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
- tcg_temp_free_i32(r_size);
- tcg_temp_free_i32(r_asi);
+
+ switch (da.type) {
+ case GET_ASI_EXCP:
+ break;
+ default:
+ {
+ TCGv_i32 r_asi = tcg_const_i32(da.asi);
+ TCGv_i32 r_size = tcg_const_i32(8);
+
+ save_state(dc);
+ gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
+ tcg_temp_free_i32(r_size);
+ tcg_temp_free_i32(r_asi);
+ }
+ break;
+ }
+
tcg_temp_free_i64(t64);
}
#endif
@@ -4676,87 +4815,32 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x10: /* lda, V9 lduwa, load word alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 0);
break;
case 0x11: /* lduba, load unsigned byte alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 0);
break;
case 0x12: /* lduha, load unsigned halfword alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 0);
break;
case 0x13: /* ldda, load double word alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- if (rd & 1)
+ if (rd & 1) {
goto illegal_insn;
- save_state(dc);
+ }
gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
goto skip_move;
case 0x19: /* ldsba, load signed byte alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 1);
break;
case 0x1a: /* ldsha, load signed halfword alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 1);
break;
case 0x1d: /* ldstuba -- XXX: should be atomically */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
break;
case 0x1f: /* swapa, swap reg with alt. memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
cpu_src1 = gen_load_gpr(dc, rd);
gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
break;
@@ -4778,11 +4862,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x18: /* V9 ldswa */
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 1);
break;
case 0x1b: /* V9 ldxa */
- save_state(dc);
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 8, 0);
break;
case 0x2d: /* V9 prefetch, no effect */
@@ -4791,7 +4873,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- save_state(dc);
gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
gen_update_fprs_dirty(rd);
goto skip_move;
@@ -4799,7 +4880,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- save_state(dc);
gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
gen_update_fprs_dirty(DFPREG(rd));
goto skip_move;
@@ -4810,7 +4890,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
- save_state(dc);
gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
gen_update_fprs_dirty(QFPREG(rd));
goto skip_move;
@@ -4918,51 +4997,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x14: /* sta, V9 stwa, store word alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_st_asi(dc, cpu_val, cpu_addr, insn, 4);
- dc->npc = DYNAMIC_PC;
break;
case 0x15: /* stba, store byte alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_st_asi(dc, cpu_val, cpu_addr, insn, 1);
- dc->npc = DYNAMIC_PC;
break;
case 0x16: /* stha, store halfword alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
- goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- save_state(dc);
gen_st_asi(dc, cpu_val, cpu_addr, insn, 2);
- dc->npc = DYNAMIC_PC;
break;
case 0x17: /* stda, store double word alternate */
-#ifndef TARGET_SPARC64
- if (IS_IMM)
+ if (rd & 1) {
goto illegal_insn;
- if (!supervisor(dc))
- goto priv_insn;
-#endif
- if (rd & 1)
- goto illegal_insn;
- else {
- save_state(dc);
- gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
}
+ gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
break;
#endif
#ifdef TARGET_SPARC64
@@ -4971,9 +5018,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
break;
case 0x1e: /* V9 stxa */
- save_state(dc);
gen_st_asi(dc, cpu_val, cpu_addr, insn, 8);
- dc->npc = DYNAMIC_PC;
break;
#endif
default:
@@ -5090,13 +5135,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x3c: /* V9 or LEON3 casa */
#ifndef TARGET_SPARC64
CHECK_IU_FEATURE(dc, CASA);
- if (IS_IMM) {
- goto illegal_insn;
- }
- /* LEON3 allows CASA from user space with ASI 0xa */
- if ((GET_FIELD(insn, 19, 26) != 0xa) && !supervisor(dc)) {
- goto priv_insn;
- }
#endif
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
--
2.5.0
next prev parent reply other threads:[~2016-02-23 21:12 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-23 21:11 [Qemu-devel] [PATCH v2 00/24] target-sparc improvements Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 01/24] target-sparc: Mark more flags for helpers Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 02/24] target-sparc: Remove softint as a TCG global Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 03/24] target-sparc: Store mmu index in TB flags Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 04/24] target-sparc: Create gen_exception Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 05/24] target-sparc: Unify asi handling between 32 and 64-bit Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 06/24] target-sparc: Store %asi in TB flags Richard Henderson
2016-02-23 21:11 ` Richard Henderson [this message]
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 08/24] target-sparc: Pass TCGMemOp to gen_ld/st_asi Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 09/24] target-sparc: Import linux/arch/sparc/include/uapi/asm/asi.h Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 10/24] target-sparc: Add UA2005 defines to asi.h Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 11/24] target-sparc: Use defines from asi.h Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 12/24] target-sparc: Directly implement easy ld/st asis Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 13/24] target-sparc: Use QT0 to return results from ldda Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 14/24] target-sparc: Introduce gen_check_align Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 15/24] target-sparc: Directly implement easy ldd/std asis Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 16/24] target-sparc: Fix obvious error in ASI_M_BFILL Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 17/24] target-sparc: Pass TCGMemOp constants to helper_ld/st_asi Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 18/24] target-sparc: Directly implement easy ldf/stf asis Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 19/24] target-sparc: Directly implement block and short " Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 20/24] target-sparc: Remove helper_ldf_asi, helper_stf_asi Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 21/24] target-sparc: Use explicit writes to cpu_fsr Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 22/24] target-sparc: Use cpu_fsr in stfsr Richard Henderson
2016-02-23 21:11 ` [Qemu-devel] [PATCH v2 23/24] target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptions Richard Henderson
2016-02-23 21:12 ` [Qemu-devel] [PATCH v2 24/24] target-sparc: Elide duplicate updates to fprs Richard Henderson
2016-02-26 9:44 ` [Qemu-devel] [PATCH v2 00/24] target-sparc improvements Mark Cave-Ayland
2016-03-11 19:10 ` Artyom Tarasenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1456261920-29900-8-git-send-email-rth@twiddle.net \
--to=rth@twiddle.net \
--cc=atar4qemu@gmail.com \
--cc=mark.cave-ayland@ilande.co.uk \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.