From: Marc Zyngier <marc.zyngier@arm.com>
To: Christoffer Dall <christoffer.dall@linaro.org>
Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 09/12] arm64: KVM: vgic-v3: Save maintenance interrupt state only if required
Date: Mon, 7 Mar 2016 09:33:31 +0000 [thread overview]
Message-ID: <1457343214-19547-10-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1457343214-19547-1-git-send-email-marc.zyngier@arm.com>
Next on our list of useless accesses is the maintenance interrupt
status registers (ICH_MISR_EL2, ICH_EISR_EL2).
It is pointless to save them if we haven't asked for a maintenance
interrupt the first place, which can only happen for two reasons:
- Underflow: ICH_HCR_UIE will be set,
- EOI: ICH_LR_EOI will be set.
These conditions can be checked on the in-memory copies of the regs.
Should any of these two condition be valid, we must read GICH_MISR.
We can then check for ICH_MISR_EOI, and only when set read
ICH_EISR_EL2.
This means that in most case, we don't have to save them at all.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kvm/hyp/vgic-v3-sr.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
index e596945..61a5e46 100644
--- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
+++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
@@ -131,6 +131,35 @@ static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
}
}
+static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu, int nr_lr)
+{
+ struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
+ int i;
+ bool expect_mi;
+
+ expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE);
+
+ for (i = 0; i < nr_lr; i++) {
+ if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
+ continue;
+
+ expect_mi |= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) &&
+ (cpu_if->vgic_lr[i] & ICH_LR_EOI));
+ }
+
+ if (expect_mi) {
+ cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
+
+ if (cpu_if->vgic_misr & ICH_MISR_EOI)
+ cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
+ else
+ cpu_if->vgic_eisr = 0;
+ } else {
+ cpu_if->vgic_misr = 0;
+ cpu_if->vgic_eisr = 0;
+ }
+}
+
void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
{
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
@@ -148,8 +177,6 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
int i;
u32 max_lr_idx, nr_pri_bits;
- cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
- cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
write_gicreg(0, ICH_HCR_EL2);
@@ -157,6 +184,8 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
max_lr_idx = vtr_to_max_lr_idx(val);
nr_pri_bits = vtr_to_nr_pri_bits(val);
+ save_maint_int_state(vcpu, max_lr_idx + 1);
+
for (i = 0; i <= max_lr_idx; i++) {
if (vcpu->arch.vgic_cpu.live_lrs & (1UL << i))
cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
--
2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 09/12] arm64: KVM: vgic-v3: Save maintenance interrupt state only if required
Date: Mon, 7 Mar 2016 09:33:31 +0000 [thread overview]
Message-ID: <1457343214-19547-10-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1457343214-19547-1-git-send-email-marc.zyngier@arm.com>
Next on our list of useless accesses is the maintenance interrupt
status registers (ICH_MISR_EL2, ICH_EISR_EL2).
It is pointless to save them if we haven't asked for a maintenance
interrupt the first place, which can only happen for two reasons:
- Underflow: ICH_HCR_UIE will be set,
- EOI: ICH_LR_EOI will be set.
These conditions can be checked on the in-memory copies of the regs.
Should any of these two condition be valid, we must read GICH_MISR.
We can then check for ICH_MISR_EOI, and only when set read
ICH_EISR_EL2.
This means that in most case, we don't have to save them at all.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kvm/hyp/vgic-v3-sr.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c
index e596945..61a5e46 100644
--- a/arch/arm64/kvm/hyp/vgic-v3-sr.c
+++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c
@@ -131,6 +131,35 @@ static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
}
}
+static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu, int nr_lr)
+{
+ struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
+ int i;
+ bool expect_mi;
+
+ expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE);
+
+ for (i = 0; i < nr_lr; i++) {
+ if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
+ continue;
+
+ expect_mi |= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) &&
+ (cpu_if->vgic_lr[i] & ICH_LR_EOI));
+ }
+
+ if (expect_mi) {
+ cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
+
+ if (cpu_if->vgic_misr & ICH_MISR_EOI)
+ cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
+ else
+ cpu_if->vgic_eisr = 0;
+ } else {
+ cpu_if->vgic_misr = 0;
+ cpu_if->vgic_eisr = 0;
+ }
+}
+
void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
{
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
@@ -148,8 +177,6 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
int i;
u32 max_lr_idx, nr_pri_bits;
- cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
- cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
write_gicreg(0, ICH_HCR_EL2);
@@ -157,6 +184,8 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
max_lr_idx = vtr_to_max_lr_idx(val);
nr_pri_bits = vtr_to_nr_pri_bits(val);
+ save_maint_int_state(vcpu, max_lr_idx + 1);
+
for (i = 0; i <= max_lr_idx; i++) {
if (vcpu->arch.vgic_cpu.live_lrs & (1UL << i))
cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
--
2.1.4
next prev parent reply other threads:[~2016-03-07 9:34 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 9:33 [PATCH v3 00/12] Virtual GIC save/restore optimization Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 01/12] KVM: arm/arm64: vgic-v2: Avoid accessing GICH registers Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 02/12] KVM: arm/arm64: vgic-v2: Save maintenance interrupt state only if required Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 03/12] KVM: arm/arm64: vgic-v2: Move GICH_ELRSR saving to its own function Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 04/12] KVM: arm/arm64: vgic-v2: Do not save an LR known to be empty Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 05/12] KVM: arm/arm64: vgic-v2: Reset LRs at boot time Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-09 3:07 ` Christoffer Dall
2016-03-09 3:07 ` Christoffer Dall
2016-03-07 9:33 ` [PATCH v3 06/12] KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-09 3:09 ` Christoffer Dall
2016-03-09 3:09 ` Christoffer Dall
2016-03-07 9:33 ` [PATCH v3 07/12] KVM: arm/arm64: vgic-v2: Make GICD_SGIR quicker to hit Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 08/12] arm64: KVM: vgic-v3: Avoid accessing ICH registers Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier [this message]
2016-03-07 9:33 ` [PATCH v3 09/12] arm64: KVM: vgic-v3: Save maintenance interrupt state only if required Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 10/12] arm64: KVM: vgic-v3: Do not save an LR known to be empty Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-07 9:33 ` [PATCH v3 11/12] arm64: KVM: vgic-v3: Reset LRs at boot time Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
2016-03-09 3:12 ` Christoffer Dall
2016-03-09 3:12 ` Christoffer Dall
2016-03-07 9:33 ` [PATCH v3 12/12] arm64: KVM: vgic-v3: Only wipe LRs on vcpu exit Marc Zyngier
2016-03-07 9:33 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1457343214-19547-10-git-send-email-marc.zyngier@arm.com \
--to=marc.zyngier@arm.com \
--cc=christoffer.dall@linaro.org \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.