From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: Cache elsp submit register
Date: Tue, 22 Mar 2016 17:16:52 +0000 [thread overview]
Message-ID: <1458667013-13944-1-git-send-email-tvrtko.ursulin@linux.intel.com> (raw)
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Since we write four times to the same register, caching
the mmio register saves a tiny amount of generated code.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e733795b57e0..6916991bdceb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -362,6 +362,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
struct intel_engine_cs *engine = rq0->engine;
struct drm_i915_private *dev_priv = rq0->i915;
+ i915_reg_t elsp_reg = RING_ELSP(engine);
uint64_t desc[2];
if (rq1) {
@@ -375,12 +376,12 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
rq0->elsp_submitted++;
/* You must always write both descriptors in the order below. */
- I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
- I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
+ I915_WRITE_FW(elsp_reg, upper_32_bits(desc[1]));
+ I915_WRITE_FW(elsp_reg, lower_32_bits(desc[1]));
- I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
+ I915_WRITE_FW(elsp_reg, upper_32_bits(desc[0]));
/* The context is automatically loaded after the following */
- I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
+ I915_WRITE_FW(elsp_reg, lower_32_bits(desc[0]));
/* ELSP is a wo register, use another nearby reg for posting */
POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
--
1.9.1
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next reply other threads:[~2016-03-22 17:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-22 17:16 Tvrtko Ursulin [this message]
2016-03-22 17:13 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Cache elsp submit register Patchwork
2016-03-22 17:16 ` [PATCH 2/2] drm/i915: Shrink i915_gem_request_add_to_client Tvrtko Ursulin
2016-03-22 17:59 ` Chris Wilson
2016-03-23 10:10 ` Tvrtko Ursulin
2016-03-22 17:29 ` [PATCH 1/2] drm/i915: Cache elsp submit register Ville Syrjälä
2016-03-22 17:39 ` Tvrtko Ursulin
2016-03-30 15:05 ` Dave Gordon
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