From: Chanwoo Choi <cw00.choi@samsung.com> To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v8 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Date: Fri, 08 Apr 2016 13:25:05 +0900 [thread overview] Message-ID: <1460089509-16260-17-git-send-email-cw00.choi@samsung.com> (raw) In-Reply-To: <1460089509-16260-1-git-send-email-cw00.choi@samsung.com> This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- arch/arm/boot/dts/exynos4210.dtsi | 159 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index c1cb8df6da07..2d9b02967105 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -257,6 +257,165 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; }; &gic { -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: cw00.choi@samsung.com (Chanwoo Choi) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Date: Fri, 08 Apr 2016 13:25:05 +0900 [thread overview] Message-ID: <1460089509-16260-17-git-send-email-cw00.choi@samsung.com> (raw) In-Reply-To: <1460089509-16260-1-git-send-email-cw00.choi@samsung.com> This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> --- arch/arm/boot/dts/exynos4210.dtsi | 159 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index c1cb8df6da07..2d9b02967105 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -257,6 +257,165 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp at 267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp at 400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp at 160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp at 200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp at 160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp at 160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp at 200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; }; &gic { -- 1.9.1
next prev parent reply other threads:[~2016-04-08 4:27 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-04-08 4:24 [PATCH v8 00/20] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 01/20] PM / devfreq: exynos: Add generic exynos bus frequency driver Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 02/20] PM / devfreq: exynos: Add documentation for " Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-11 15:40 ` Rob Herring 2016-04-11 15:40 ` Rob Herring 2016-04-11 20:25 ` Chanwoo Choi 2016-04-11 20:25 ` Chanwoo Choi 2016-04-14 5:10 ` Chanwoo Choi 2016-04-14 5:10 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 03/20] PM / devfreq: Add devfreq_get_devfreq_by_phandle() Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 04/20] PM / devfreq: Add new DEVFREQ_TRANSITION_NOTIFIER notifier Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 05/20] PM / devfreq: Add new passive governor Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 06/20] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using " Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 07/20] PM / devfreq: exynos: Update documentation for bus devices " Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 08/20] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 09/20] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:24 ` [PATCH v8 10/20] MAINTAINERS: Add samsung bus frequency driver entry Chanwoo Choi 2016-04-08 4:24 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 11/20] ARM: dts: Add DMC bus node for Exynos3250 Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 12/20] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 13/20] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 14/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 15/20] ARM: dts: Add bus nodes using VDD_INT " Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi [this message] 2016-04-08 4:25 ` [PATCH v8 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 17/20] ARM: dts: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 18/20] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 19/20] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` [PATCH v8 20/20] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3 Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi 2016-04-08 4:25 ` Chanwoo Choi
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