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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 03/12] drm/i915: Clear VLV_IIR after PIPESTAT
Date: Wed, 13 Apr 2016 21:19:49 +0300	[thread overview]
Message-ID: <1460571598-24452-4-git-send-email-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <1460571598-24452-1-git-send-email-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On VLV/CHV VLV_IIR is not double double buffered, and it doesn't detect
edges from PIPESTAT & co. like it does on gen4. Instead it just
directly latches the level from PIPESTAT & co. That means we must clear
VLV_IIR after PIPESTAT & co. or else we'll get a spurious bit in VLV_IIR
every single time.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 36 +++++++++++++++++++++---------------
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f96a374ea624..52ccb4af5e18 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1789,12 +1789,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 			I915_WRITE(GEN6_PMIIR, pm_iir);
 
 		iir = I915_READ(VLV_IIR);
-		if (iir) {
-			/* Consume port before clearing IIR or we'll miss events */
-			if (iir & I915_DISPLAY_PORT_INTERRUPT)
-				i9xx_hpd_irq_handler(dev);
-			I915_WRITE(VLV_IIR, iir);
-		}
 
 		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 			goto out;
@@ -1805,9 +1799,20 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 			snb_gt_irq_handler(dev, dev_priv, gt_iir);
 		if (pm_iir)
 			gen6_rps_irq_handler(dev_priv, pm_iir);
+
+		if (iir & I915_DISPLAY_PORT_INTERRUPT)
+			i9xx_hpd_irq_handler(dev);
+
 		/* Call regardless, as some status bits might not be
 		 * signalled in iir */
 		valleyview_pipestat_irq_handler(dev, iir);
+
+		/*
+		 * VLV_IIR is single buffered, and reflects the level
+		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
+		 */
+		if (iir)
+			I915_WRITE(VLV_IIR, iir);
 	}
 
 out:
@@ -1840,21 +1845,22 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 		I915_WRITE(GEN8_MASTER_IRQ, 0);
 
-		/* Find, clear, then process each source of interrupt */
-
-		if (iir) {
-			/* Consume port before clearing IIR or we'll miss events */
-			if (iir & I915_DISPLAY_PORT_INTERRUPT)
-				i9xx_hpd_irq_handler(dev);
-			I915_WRITE(VLV_IIR, iir);
-		}
-
 		gen8_gt_irq_handler(dev_priv, master_ctl);
 
+		if (iir & I915_DISPLAY_PORT_INTERRUPT)
+			i9xx_hpd_irq_handler(dev);
+
 		/* Call regardless, as some status bits might not be
 		 * signalled in iir */
 		valleyview_pipestat_irq_handler(dev, iir);
 
+		/*
+		 * VLV_IIR is single buffered, and reflects the level
+		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
+		 */
+		if (iir)
+			I915_WRITE(VLV_IIR, iir);
+
 		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 		POSTING_READ(GEN8_MASTER_IRQ);
 	} while (0);
-- 
2.7.4

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  parent reply	other threads:[~2016-04-13 18:20 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-13 18:19 [PATCH 00/12] drm/i915: VLV/CHV irq handler fixes ville.syrjala
2016-04-13 18:19 ` [PATCH 01/12] drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently ville.syrjala
2016-04-13 18:19 ` [PATCH 02/12] drm/i915: Set up VLV_MASTER_IER consistently ville.syrjala
2016-04-13 18:19 ` ville.syrjala [this message]
2016-04-13 18:19 ` [PATCH 04/12] drm/i915: Clear VLV_MASTER_IER around irq processing ville.syrjala
2016-04-13 18:19 ` [PATCH 05/12] drm/i915: Clear VLV_IER " ville.syrjala
2016-04-13 20:53   ` Chris Wilson
2016-04-14  8:22     ` Ville Syrjälä
2016-04-14  8:32       ` Chris Wilson
2016-04-14  8:49         ` Ville Syrjälä
2016-04-14  9:36   ` Chris Wilson
2016-04-14 12:30     ` Ville Syrjälä
2016-04-14 12:47   ` Mika Kuoppala
2016-04-15  7:32     ` Mika Kuoppala
2016-04-13 18:19 ` [PATCH 06/12] drm/i915: Eliminate loop from VLV irq handler ville.syrjala
2016-04-13 18:19 ` [PATCH 07/12] drm/i915: Move variables to narrower scope in VLV/CHV irq handlers ville.syrjala
2016-04-13 18:19 ` [PATCH 08/12] drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler() ville.syrjala
2016-04-13 18:19 ` [PATCH 09/12] drm/i915: Split VLV/CVH PIPESTAT handling into ack+handler ville.syrjala
2016-04-13 18:19 ` [PATCH 10/12] drm/i915: Move gt/pm irq handling out from irq disabled section on VLV ville.syrjala
2016-04-13 18:19 ` [PATCH 11/12] drm/i915: Eliminate passing dev+dev_priv to {snb, ilk}_gt_irq_handler() ville.syrjala
2016-04-13 21:02   ` Daniel Vetter
2016-04-13 18:19 ` [PATCH 12/12] drm/i915: Split gen8_gt_irq_handler into ack+handle ville.syrjala

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