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From: vladimir.murzin@arm.com (Vladimir Murzin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC 02/10] ARM: V7M: Make read_cpuid() generally available on V7M.
Date: Thu, 21 Apr 2016 09:18:14 +0100	[thread overview]
Message-ID: <1461226702-27160-3-git-send-email-vladimir.murzin@arm.com> (raw)
In-Reply-To: <1461226702-27160-1-git-send-email-vladimir.murzin@arm.com>

From: Jonathan Austin <jonathan.austin@arm.com>

Previously V7M had a custom definition for read_cpuid_id that didn't use the
underlying read_cpuid() macro and a stub definition for read_cpuid().

This requires a custom specialisation for each of the CPUID_* registers, and
as more than just CPUID_ID may be implemented in the future this doesn't
make much sense.

This patch creates a generic implementation of read_cpuid for V7M and
removes the custom read_cpuid_id implementation.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/include/asm/cputype.h |   50 ++++++++++++++++++++++------------------
 1 file changed, 28 insertions(+), 22 deletions(-)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index b23c6c8..2d46425 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -4,15 +4,15 @@
 #include <linux/stringify.h>
 #include <linux/kernel.h>
 
-#define CPUID_ID	0
-#define CPUID_CACHETYPE	1
-#define CPUID_TCM	2
-#define CPUID_TLBTYPE	3
-#define CPUID_MPUIR	4
-#define CPUID_MPIDR	5
-#define CPUID_REVIDR	6
-
 #ifdef CONFIG_CPU_V7M
+
+#define CPUID_ID	0x0
+#define CPUID_CACHETYPE	-1
+#define CPUID_TCM	-1
+#define CPUID_TLBTYPE	-1
+#define CPUID_MPIDR	-1
+#define CPUID_REVIDR	-1
+
 #define CPUID_EXT_PFR0	0x40
 #define CPUID_EXT_PFR1	0x44
 #define CPUID_EXT_DFR0	0x48
@@ -28,6 +28,14 @@
 #define CPUID_EXT_ISAR4	0x70
 #define CPUID_EXT_ISAR5	0x74
 #else
+#define CPUID_ID	0
+#define CPUID_CACHETYPE	1
+#define CPUID_TCM	2
+#define CPUID_TLBTYPE	3
+#define CPUID_MPUIR	4
+#define CPUID_MPIDR	5
+#define CPUID_REVIDR	6
+
 #define CPUID_EXT_PFR0	"c1, 0"
 #define CPUID_EXT_PFR1	"c1, 1"
 #define CPUID_EXT_DFR0	"c1, 2"
@@ -114,11 +122,16 @@ extern unsigned int processor_id;
 #include <asm/io.h>
 #include <asm/v7m.h>
 
-#define read_cpuid(reg)							\
-	({								\
-		WARN_ON_ONCE(1);					\
-		0;							\
-	})
+static inline unsigned int __attribute_const__ read_cpuid(unsigned offset)
+{
+	switch (offset) {
+	case CPUID_ID:
+		return readl(BASEADDR_V7M_SCB + offset);
+	default:
+		WARN_ON_ONCE(1);
+		return 0;
+	}
+}
 
 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 {
@@ -141,7 +154,7 @@ static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 
 #endif /* ifdef CONFIG_CPU_CP15 / else */
 
-#ifdef CONFIG_CPU_CP15
+#if defined(CONFIG_CPU_CP15) || defined(CONFIG_CPU_V7M)
 /*
  * The CPU ID never changes at run time, so we might as well tell the
  * compiler that it's constant.  Use this function to read the CPU ID
@@ -152,14 +165,7 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
 	return read_cpuid(CPUID_ID);
 }
 
-#elif defined(CONFIG_CPU_V7M)
-
-static inline unsigned int __attribute_const__ read_cpuid_id(void)
-{
-	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
-}
-
-#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
+#else /* if defined(CONFIG_CPU_CP15) || defined(CONFIG_CPU_V7M) */
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
-- 
1.7.9.5

  parent reply	other threads:[~2016-04-21  8:18 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-21  8:18 [PATCH RFC 00/10] ARM: V7M: Support caches Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 01/10] ARM: factor out CSSELR/CCSIDR operations that use cp15 directly Vladimir Murzin
2016-04-21  8:18 ` Vladimir Murzin [this message]
2016-04-21  8:18 ` [PATCH RFC 03/10] ARM: V7M: Add addresses for mem-mapped V7M cache operations Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 04/10] ARM: V7M: Add support for reading the CTR with CPUID_CACHETYPE Vladimir Murzin
2016-04-27  9:13   ` Russell King - ARM Linux
2016-04-27 12:18     ` Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 05/10] ARM: Extract cp15 operations from cache flush code Vladimir Murzin
2016-04-27  9:21   ` Russell King - ARM Linux
2016-04-27 12:24     ` Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 06/10] ARM: V7M: Implement cache macros for V7M Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 07/10] ARM: V7M: fix notrace variant of save_and_disable_irqs Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 08/10] ARM: V7M: Wire up caches for V7M processors with cache support Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 09/10] ARM: V7M: Indirect proc_info construction for V7M CPUs Vladimir Murzin
2016-04-21  8:18 ` [PATCH RFC 10/10] ARM: V7M: Add support for the Cortex-M7 processor Vladimir Murzin
2016-05-26  8:05 ` [PATCH RFC 00/10] ARM: V7M: Support caches Alexandre Torgue
2016-06-01 13:03   ` Vladimir Murzin

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