From: Douglas Anderson <dianders@chromium.org> To: Heiko Stuebner <heiko@sntech.de>, mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-rockchip@lists.infradead.org, shawn.lin@rock-chips.com, zhengxing@rock-chips.com, Douglas Anderson <dianders@chromium.org>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] clk: rockchip: fix the rk3399 sdmmc sample shift Date: Thu, 12 May 2016 11:03:17 -0700 [thread overview] Message-ID: <1463076197-15900-2-git-send-email-dianders@chromium.org> (raw) In-Reply-To: <1463076197-15900-1-git-send-email-dianders@chromium.org> Just like every other Rockhip device, the MMC "_sample" clocks should have a shift of 0, not a shift of 1. The rk3399 TRM agrees. Presumably these values were set to 0 because of a typo. Things _sorta_ would have worked with the incorrect sample phase shift because of the register layout but wouldn't have been ideal and we would have skipped lots of phases. Also: we would never actually enabled the fine delay unless we happened to have 128 or more delay elements. This is expected behavior before this patch: * Try to set: 0 degrees + 1 delay elements Actually get: 0 degrees + 0 delay elements * Try to set: 90 degrees + 0 delay elements Actually get: 180 degrees + 0 delay elements * Try to set: 180 degrees + 0 delay elements Actually get: 0 degrees + 0 delay elements * Try to set: 270 degrees + 0 delay elements Actually get: 180 degrees + 0 delay elements * Try to set: 0 degrees + 129 delay elements Actually get: 0 degrees + 2 delay elements * Try to set: 180 degrees + 129 delay elements Actually get: 0 degrees + 3 delay elements * Try to set: 0 degrees + 130 delay elements Actually get: 0 degrees + 4 delay elements I verified that old code had a problem by turning on debug printouts and seeing that the old code would report this for one SD card I had: Good phase range 347-101 (115 len) Good phase range 202-326 (125 len) After my fix, it went down to one big good range for the same card. This is more expected: Good phase range 189-1 (173 len) Good phase range 82-85 (4 len) Good phase range 166-168 (3 len) Signed-off-by: Douglas Anderson <dianders@chromium.org> --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 291543f52caa..14ff3e109e1e 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -895,10 +895,10 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(6), 1, GFLAGS), MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 0), MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), - MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 0), /* pcie */ COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, -- 2.8.0.rc3.226.g39d4020
WARNING: multiple messages have this Message-ID (diff)
From: dianders@chromium.org (Douglas Anderson) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] clk: rockchip: fix the rk3399 sdmmc sample shift Date: Thu, 12 May 2016 11:03:17 -0700 [thread overview] Message-ID: <1463076197-15900-2-git-send-email-dianders@chromium.org> (raw) In-Reply-To: <1463076197-15900-1-git-send-email-dianders@chromium.org> Just like every other Rockhip device, the MMC "_sample" clocks should have a shift of 0, not a shift of 1. The rk3399 TRM agrees. Presumably these values were set to 0 because of a typo. Things _sorta_ would have worked with the incorrect sample phase shift because of the register layout but wouldn't have been ideal and we would have skipped lots of phases. Also: we would never actually enabled the fine delay unless we happened to have 128 or more delay elements. This is expected behavior before this patch: * Try to set: 0 degrees + 1 delay elements Actually get: 0 degrees + 0 delay elements * Try to set: 90 degrees + 0 delay elements Actually get: 180 degrees + 0 delay elements * Try to set: 180 degrees + 0 delay elements Actually get: 0 degrees + 0 delay elements * Try to set: 270 degrees + 0 delay elements Actually get: 180 degrees + 0 delay elements * Try to set: 0 degrees + 129 delay elements Actually get: 0 degrees + 2 delay elements * Try to set: 180 degrees + 129 delay elements Actually get: 0 degrees + 3 delay elements * Try to set: 0 degrees + 130 delay elements Actually get: 0 degrees + 4 delay elements I verified that old code had a problem by turning on debug printouts and seeing that the old code would report this for one SD card I had: Good phase range 347-101 (115 len) Good phase range 202-326 (125 len) After my fix, it went down to one big good range for the same card. This is more expected: Good phase range 189-1 (173 len) Good phase range 82-85 (4 len) Good phase range 166-168 (3 len) Signed-off-by: Douglas Anderson <dianders@chromium.org> --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 291543f52caa..14ff3e109e1e 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -895,10 +895,10 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(6), 1, GFLAGS), MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 0), MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), - MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 0), /* pcie */ COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, -- 2.8.0.rc3.226.g39d4020
next prev parent reply other threads:[~2016-05-12 18:03 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-05-12 18:03 [PATCH 1/2] Revert "clk: rockchip: reset init state before mmc card initialization" Douglas Anderson 2016-05-12 18:03 ` Douglas Anderson 2016-05-12 18:03 ` Douglas Anderson [this message] 2016-05-12 18:03 ` [PATCH 2/2] clk: rockchip: fix the rk3399 sdmmc sample shift Douglas Anderson 2016-05-12 23:10 ` Brian Norris 2016-05-12 23:10 ` Brian Norris 2016-05-12 23:47 ` Shawn Lin 2016-05-12 23:47 ` Shawn Lin 2016-05-13 4:36 ` Doug Anderson 2016-05-13 4:36 ` Doug Anderson 2016-05-13 4:36 ` Doug Anderson 2016-05-13 4:36 ` Doug Anderson 2016-05-13 7:46 ` Shawn Lin 2016-05-13 7:46 ` Shawn Lin 2016-05-13 7:46 ` Shawn Lin 2016-05-13 16:38 ` Doug Anderson 2016-05-13 16:38 ` Doug Anderson 2016-05-13 16:38 ` Doug Anderson 2016-05-12 23:41 ` [PATCH 1/2] Revert "clk: rockchip: reset init state before mmc card initialization" Heiko Stuebner 2016-05-12 23:41 ` Heiko Stuebner 2016-05-13 2:11 ` Doug Anderson 2016-05-13 2:11 ` Doug Anderson 2016-05-13 2:11 ` Doug Anderson 2016-05-13 0:19 ` Shawn Lin 2016-05-13 0:19 ` Shawn Lin 2016-05-17 21:56 ` Heiko Stuebner 2016-05-17 21:56 ` Heiko Stuebner 2016-05-18 7:25 ` Shawn Lin 2016-05-18 7:25 ` Shawn Lin
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