From: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> To: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org, treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, stepanm-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org Subject: [PATCH V4 6/7] iommu/msm: Use writel_relaxed and add a barrier Date: Mon, 16 May 2016 12:19:00 +0530 [thread overview] Message-ID: <1463381341-30498-7-git-send-email-sricharan@codeaurora.org> (raw) In-Reply-To: <1463381341-30498-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> While using the generic pagetable ops the tlb maintenance operation gets completed in the sync callback. So use writel_relaxed for all register access and add a mb() at appropriate places. Signed-off-by: Sricharan R <sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> --- drivers/iommu/msm_iommu.c | 11 ++++++++--- drivers/iommu/msm_iommu_hw-8xxx.h | 7 ++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index f7b4c11..1240a5a 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -124,6 +124,7 @@ static void msm_iommu_reset(void __iomem *base, int ncb) SET_TLBLKCR(base, ctx, 0); SET_CONTEXTIDR(base, ctx, 0); } + mb(); /* sync */ } static void __flush_iotlb(void *cookie) @@ -143,6 +144,7 @@ static void __flush_iotlb(void *cookie) __disable_clocks(iommu); } + mb(); /* sync */ fail: return; } @@ -181,7 +183,7 @@ fail: static void __flush_iotlb_sync(void *cookie) { - /* To avoid a null function pointer */ + mb(); /* sync */ } static const struct iommu_gather_ops msm_iommu_gather_ops = { @@ -235,6 +237,7 @@ static void config_mids(struct msm_iommu_dev *iommu, /* Set security bit override to be Non-secure */ SET_NSCFG(iommu->base, mid, 3); } + mb(); /* sync */ } static void __reset_context(void __iomem *base, int ctx) @@ -257,6 +260,7 @@ static void __reset_context(void __iomem *base, int ctx) SET_TLBFLPTER(base, ctx, 0); SET_TLBSLPTER(base, ctx, 0); SET_TLBLKCR(base, ctx, 0); + mb(); /* sync */ } static void __program_context(void __iomem *base, int ctx, @@ -305,6 +309,7 @@ static void __program_context(void __iomem *base, int ctx, /* Enable the MMU */ SET_M(base, ctx, 1); + mb(); /* sync */ } static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) @@ -500,7 +505,7 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, /* Invalidate context TLB */ SET_CTX_TLBIALL(iommu->base, master->num, 0); SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); - + mb(); /* sync */ par = GET_PAR(iommu->base, master->num); /* We are dealing with a supersection */ @@ -714,7 +719,7 @@ static int msm_iommu_probe(struct platform_device *pdev) par = GET_PAR(iommu->base, 0); SET_V2PCFG(iommu->base, 0, 0); SET_M(iommu->base, 0, 0); - + mb(); /* sync */ if (!par) { pr_err("Invalid PAR value detected\n"); ret = -ENODEV; diff --git a/drivers/iommu/msm_iommu_hw-8xxx.h b/drivers/iommu/msm_iommu_hw-8xxx.h index 84ba5739..161036c 100644 --- a/drivers/iommu/msm_iommu_hw-8xxx.h +++ b/drivers/iommu/msm_iommu_hw-8xxx.h @@ -24,10 +24,10 @@ #define GET_CTX_REG(reg, base, ctx) \ (readl((base) + (reg) + ((ctx) << CTX_SHIFT))) -#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg))) +#define SET_GLOBAL_REG(reg, base, val) writel_relaxed((val), ((base) + (reg))) #define SET_CTX_REG(reg, base, ctx, val) \ - writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) + writel_relaxed((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) /* Wrappers for numbered registers */ #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) @@ -48,7 +48,8 @@ #define SET_FIELD(addr, mask, shift, v) \ do { \ int t = readl(addr); \ - writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\ + writel_relaxed((t & ~((mask) << (shift))) + \ + (((v) & (mask)) << (shift)), addr);\ } while (0) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: sricharan@codeaurora.org (Sricharan R) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V4 6/7] iommu/msm: Use writel_relaxed and add a barrier Date: Mon, 16 May 2016 12:19:00 +0530 [thread overview] Message-ID: <1463381341-30498-7-git-send-email-sricharan@codeaurora.org> (raw) In-Reply-To: <1463381341-30498-1-git-send-email-sricharan@codeaurora.org> While using the generic pagetable ops the tlb maintenance operation gets completed in the sync callback. So use writel_relaxed for all register access and add a mb() at appropriate places. Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- drivers/iommu/msm_iommu.c | 11 ++++++++--- drivers/iommu/msm_iommu_hw-8xxx.h | 7 ++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index f7b4c11..1240a5a 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -124,6 +124,7 @@ static void msm_iommu_reset(void __iomem *base, int ncb) SET_TLBLKCR(base, ctx, 0); SET_CONTEXTIDR(base, ctx, 0); } + mb(); /* sync */ } static void __flush_iotlb(void *cookie) @@ -143,6 +144,7 @@ static void __flush_iotlb(void *cookie) __disable_clocks(iommu); } + mb(); /* sync */ fail: return; } @@ -181,7 +183,7 @@ fail: static void __flush_iotlb_sync(void *cookie) { - /* To avoid a null function pointer */ + mb(); /* sync */ } static const struct iommu_gather_ops msm_iommu_gather_ops = { @@ -235,6 +237,7 @@ static void config_mids(struct msm_iommu_dev *iommu, /* Set security bit override to be Non-secure */ SET_NSCFG(iommu->base, mid, 3); } + mb(); /* sync */ } static void __reset_context(void __iomem *base, int ctx) @@ -257,6 +260,7 @@ static void __reset_context(void __iomem *base, int ctx) SET_TLBFLPTER(base, ctx, 0); SET_TLBSLPTER(base, ctx, 0); SET_TLBLKCR(base, ctx, 0); + mb(); /* sync */ } static void __program_context(void __iomem *base, int ctx, @@ -305,6 +309,7 @@ static void __program_context(void __iomem *base, int ctx, /* Enable the MMU */ SET_M(base, ctx, 1); + mb(); /* sync */ } static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) @@ -500,7 +505,7 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, /* Invalidate context TLB */ SET_CTX_TLBIALL(iommu->base, master->num, 0); SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); - + mb(); /* sync */ par = GET_PAR(iommu->base, master->num); /* We are dealing with a supersection */ @@ -714,7 +719,7 @@ static int msm_iommu_probe(struct platform_device *pdev) par = GET_PAR(iommu->base, 0); SET_V2PCFG(iommu->base, 0, 0); SET_M(iommu->base, 0, 0); - + mb(); /* sync */ if (!par) { pr_err("Invalid PAR value detected\n"); ret = -ENODEV; diff --git a/drivers/iommu/msm_iommu_hw-8xxx.h b/drivers/iommu/msm_iommu_hw-8xxx.h index 84ba5739..161036c 100644 --- a/drivers/iommu/msm_iommu_hw-8xxx.h +++ b/drivers/iommu/msm_iommu_hw-8xxx.h @@ -24,10 +24,10 @@ #define GET_CTX_REG(reg, base, ctx) \ (readl((base) + (reg) + ((ctx) << CTX_SHIFT))) -#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg))) +#define SET_GLOBAL_REG(reg, base, val) writel_relaxed((val), ((base) + (reg))) #define SET_CTX_REG(reg, base, ctx, val) \ - writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) + writel_relaxed((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) /* Wrappers for numbered registers */ #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) @@ -48,7 +48,8 @@ #define SET_FIELD(addr, mask, shift, v) \ do { \ int t = readl(addr); \ - writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\ + writel_relaxed((t & ~((mask) << (shift))) + \ + (((v) & (mask)) << (shift)), addr);\ } while (0) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2016-05-16 6:49 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-05-16 6:48 [PATCH V4 0/7] iommu/msm: Add DT adaptation and generic bindings support Sricharan R 2016-05-16 6:48 ` Sricharan R 2016-05-16 6:48 ` [PATCH V4 1/7] iommu/msm: Add DT adaptation Sricharan R 2016-05-16 6:48 ` Sricharan R [not found] ` <1463381341-30498-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-05-16 6:48 ` [PATCH V4 2/7] documentation: iommu: Add bindings for msm,iommu-v0 ip Sricharan R 2016-05-16 6:48 ` [PATCH V4 2/7] documentation: iommu: Add bindings for msm, iommu-v0 ip Sricharan R [not found] ` <1463381341-30498-3-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2016-05-16 16:44 ` [PATCH V4 2/7] documentation: iommu: Add bindings for msm,iommu-v0 ip Rob Herring 2016-05-16 16:44 ` Rob Herring 2016-05-18 12:08 ` Sricharan 2016-05-18 12:08 ` [PATCH V4 2/7] documentation: iommu: Add bindings for msm, iommu-v0 ip Sricharan 2016-05-16 6:48 ` [PATCH V4 3/7] iommu/msm: Move the contents from msm_iommu_dev.c to msm_iommu.c Sricharan R 2016-05-16 6:48 ` Sricharan R 2016-05-16 6:48 ` [PATCH V4 4/7] iommu/msm: Add support for generic master bindings Sricharan R 2016-05-16 6:48 ` Sricharan R 2016-05-16 6:48 ` [PATCH V4 5/7] iommu/msm: use generic ARMV7S short descriptor pagetable ops Sricharan R 2016-05-16 6:48 ` Sricharan R 2016-05-16 6:49 ` Sricharan R [this message] 2016-05-16 6:49 ` [PATCH V4 6/7] iommu/msm: Use writel_relaxed and add a barrier Sricharan R 2016-05-17 13:52 ` Arnd Bergmann 2016-05-17 13:52 ` Arnd Bergmann 2016-05-18 12:07 ` Sricharan 2016-05-18 12:07 ` Sricharan 2016-05-18 12:15 ` Arnd Bergmann 2016-05-18 12:15 ` Arnd Bergmann 2016-05-18 12:33 ` Sricharan 2016-05-18 12:33 ` Sricharan 2016-05-20 11:18 ` Sricharan 2016-05-20 11:18 ` Sricharan 2016-05-16 6:49 ` [PATCH V4 7/7] iommu/msm: Remove driver BROKEN Sricharan R 2016-05-16 6:49 ` Sricharan R
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