From: <honghui.zhang@mediatek.com>
To: <joro@8bytes.org>, <treding@nvidia.com>, <mark.rutland@arm.com>,
<matthias.bgg@gmail.com>, <robh@kernel.org>,
<robin.murphy@arm.com>
Cc: <p.zabel@pengutronix.de>, <devicetree@vger.kernel.org>,
<pebolle@tiscali.nl>, <kendrick.hsu@mediatek.com>,
<arnd@arndb.de>, <srv_heupstream@mediatek.com>,
<catalin.marinas@arm.com>, <will.deacon@arm.com>,
<linux-kernel@vger.kernel.org>, <tfiga@google.com>,
<iommu@lists.linux-foundation.org>, <robh+dt@kernel.org>,
<djkurtz@google.com>, <kernel@pengutronix.de>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>, <l.stach@pengutronix.de>,
<yingjoe.chen@mediatek.com>, <eddie.huang@mediatek.com>,
<youlin.pei@mediatek.com>, <erin.lo@mediatek.com>,
Honghui Zhang <honghui.zhang@mediatek.com>
Subject: [PATCH 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
Date: Thu, 19 May 2016 19:49:18 +0800 [thread overview]
Message-ID: <1463658558-567-6-git-send-email-honghui.zhang@mediatek.com> (raw)
In-Reply-To: <1463658558-567-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..363de0d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -16,6 +16,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
@@ -160,6 +161,16 @@
clock-names = "system-clk", "rtc-clk";
};
+ smi_common: smi@1000c000 {
+ compatible = "mediatek,mt2701-smi-common";
+ reg = <0 0x1000c000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_SMI>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi", "async";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -169,6 +180,16 @@
reg = <0 0x10200100 0 0x1c>;
};
+ iommu: mmsys_iommu@10205000 {
+ compatible = "mediatek,mt2701-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ #iommu-cells = <1>;
+ };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2701-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
@@ -234,6 +255,16 @@
status = "disabled";
};
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt2701-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -241,6 +272,16 @@
status = "disabled";
};
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_SMI_COMM>,
+ <&imgsys CLK_IMG_SMI_COMM>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
@@ -248,6 +289,16 @@
status = "disabled";
};
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKGEN>,
+ <&vdecsys CLK_VDEC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+ };
+
hifsys: syscon@1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
--
1.8.1.1.dirty
WARNING: multiple messages have this Message-ID (diff)
From: <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
To: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org,
treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
robin.murphy-5wv7dgnIgG8@public.gmane.org
Cc: catalin.marinas-5wv7dgnIgG8@public.gmane.org,
will.deacon-5wv7dgnIgG8@public.gmane.org,
youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
kendrick.hsu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
arnd-r2nGTMty4D4@public.gmane.org,
tfiga-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
djkurtz-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org
Subject: [PATCH 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
Date: Thu, 19 May 2016 19:49:18 +0800 [thread overview]
Message-ID: <1463658558-567-6-git-send-email-honghui.zhang@mediatek.com> (raw)
In-Reply-To: <1463658558-567-1-git-send-email-honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
From: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..363de0d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -16,6 +16,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
@@ -160,6 +161,16 @@
clock-names = "system-clk", "rtc-clk";
};
+ smi_common: smi@1000c000 {
+ compatible = "mediatek,mt2701-smi-common";
+ reg = <0 0x1000c000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_SMI>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi", "async";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -169,6 +180,16 @@
reg = <0 0x10200100 0 0x1c>;
};
+ iommu: mmsys_iommu@10205000 {
+ compatible = "mediatek,mt2701-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ #iommu-cells = <1>;
+ };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2701-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
@@ -234,6 +255,16 @@
status = "disabled";
};
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt2701-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -241,6 +272,16 @@
status = "disabled";
};
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_SMI_COMM>,
+ <&imgsys CLK_IMG_SMI_COMM>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
@@ -248,6 +289,16 @@
status = "disabled";
};
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKGEN>,
+ <&vdecsys CLK_VDEC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+ };
+
hifsys: syscon@1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
--
1.8.1.1.dirty
WARNING: multiple messages have this Message-ID (diff)
From: honghui.zhang@mediatek.com (honghui.zhang at mediatek.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
Date: Thu, 19 May 2016 19:49:18 +0800 [thread overview]
Message-ID: <1463658558-567-6-git-send-email-honghui.zhang@mediatek.com> (raw)
In-Reply-To: <1463658558-567-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
Add the dtsi node of iommu and smi for mt2701.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 42d5a37..363de0d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -16,6 +16,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"
@@ -160,6 +161,16 @@
clock-names = "system-clk", "rtc-clk";
};
+ smi_common: smi at 1000c000 {
+ compatible = "mediatek,mt2701-smi-common";
+ reg = <0 0x1000c000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_SMI>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi", "async";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
sysirq: interrupt-controller at 10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -169,6 +180,16 @@
reg = <0 0x10200100 0 0x1c>;
};
+ iommu: mmsys_iommu at 10205000 {
+ compatible = "mediatek,mt2701-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ #iommu-cells = <1>;
+ };
+
apmixedsys: syscon at 10209000 {
compatible = "mediatek,mt2701-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
@@ -234,6 +255,16 @@
status = "disabled";
};
+ larb0: larb at 14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
imgsys: syscon at 15000000 {
compatible = "mediatek,mt2701-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -241,6 +272,16 @@
status = "disabled";
};
+ larb2: larb at 15001000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_SMI_COMM>,
+ <&imgsys CLK_IMG_SMI_COMM>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: syscon at 16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
@@ -248,6 +289,16 @@
status = "disabled";
};
+ larb1: larb at 16010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKGEN>,
+ <&vdecsys CLK_VDEC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+ };
+
hifsys: syscon at 1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
--
1.8.1.1.dirty
next prev parent reply other threads:[~2016-05-19 11:50 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-19 11:49 [PATCH v2 0/5] MT2701 iommu support honghui.zhang
2016-05-19 11:49 ` honghui.zhang at mediatek.com
2016-05-19 11:49 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2016-05-19 11:49 ` [PATCH v2 1/5] dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi honghui.zhang
2016-05-19 11:49 ` honghui.zhang at mediatek.com
2016-05-19 11:49 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2016-05-23 15:41 ` Rob Herring
2016-05-23 15:41 ` Rob Herring
2016-05-23 15:41 ` Rob Herring
2016-05-19 11:49 ` [PATCH v2 2/5] iommu/mediatek: move the common struct into header file honghui.zhang
2016-05-19 11:49 ` honghui.zhang at mediatek.com
2016-05-19 11:49 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2016-05-19 11:49 ` [PATCH v2 3/5] memory/mediatek: add support for mt2701 honghui.zhang
2016-05-19 11:49 ` honghui.zhang at mediatek.com
2016-05-19 11:49 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2016-05-19 11:49 ` [PATCH v2 4/5] iommu/mediatek: add support for mtk iommu generation one HW honghui.zhang
2016-05-19 11:49 ` honghui.zhang at mediatek.com
2016-05-19 11:49 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
2016-05-23 19:31 ` Robin Murphy
2016-05-23 19:31 ` Robin Murphy
2016-05-23 19:31 ` Robin Murphy
2016-05-24 9:57 ` Honghui Zhang
2016-05-24 9:57 ` Honghui Zhang
2016-05-24 9:57 ` Honghui Zhang
2016-05-24 15:36 ` Robin Murphy
2016-05-24 15:36 ` Robin Murphy
2016-05-25 7:58 ` Honghui Zhang
2016-05-25 7:58 ` Honghui Zhang
2016-05-25 7:58 ` Honghui Zhang
2016-05-19 11:49 ` honghui.zhang [this message]
2016-05-19 11:49 ` [PATCH 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang at mediatek.com
2016-05-19 11:49 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
-- strict thread matches above, loose matches on Subject: below --
2016-05-09 8:00 [PATCH 0/5] MT2701 iommu support honghui.zhang
2016-05-09 8:00 ` [PATCH 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 honghui.zhang
2016-05-09 8:00 ` honghui.zhang at mediatek.com
2016-05-09 8:00 ` honghui.zhang-NuS5LvNUpcJWk0Htik3J/w
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