From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [Qemu-devel] [PATCH v3 12/24] target-sparc: Directly implement easy ld/st asis
Date: Wed, 1 Jun 2016 22:57:08 -0700 [thread overview]
Message-ID: <1464847040-22536-13-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1464847040-22536-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 104 ++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 90 insertions(+), 14 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 1d8c880..0e870d8 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1980,17 +1980,21 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
typedef enum {
GET_ASI_HELPER,
GET_ASI_EXCP,
+ GET_ASI_DIRECT,
} ASIType;
typedef struct {
ASIType type;
int asi;
+ int mem_idx;
+ TCGMemOp memop;
} DisasASI;
-static DisasASI get_asi(DisasContext *dc, int insn)
+static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
{
int asi = GET_FIELD(insn, 19, 26);
ASIType type = GET_ASI_HELPER;
+ int mem_idx = dc->mem_idx;
#ifndef TARGET_SPARC64
/* Before v9, all asis are immediate and privileged. */
@@ -2004,6 +2008,16 @@ static DisasASI get_asi(DisasContext *dc, int insn)
for LEON, which is incorrect. */
|| (asi == ASI_USERDATA
&& (dc->def->features & CPU_FEATURE_CASA))) {
+ switch (asi) {
+ case ASI_USERDATA: /* User data access */
+ mem_idx = MMU_USER_IDX;
+ type = GET_ASI_DIRECT;
+ break;
+ case ASI_KERNELDATA: /* Supervisor data access */
+ mem_idx = MMU_KERNEL_IDX;
+ type = GET_ASI_DIRECT;
+ break;
+ }
} else {
gen_exception(dc, TT_PRIV_INSN);
type = GET_ASI_EXCP;
@@ -2012,19 +2026,77 @@ static DisasASI get_asi(DisasContext *dc, int insn)
if (IS_IMM) {
asi = dc->asi;
}
+ /* With v9, all asis below 0x80 are privileged. */
+ /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
+ down that bit into DisasContext. For the moment that's ok,
+ since the direct implementations below doesn't have any ASIs
+ in the restricted [0x30, 0x7f] range, and the check will be
+ done properly in the helper. */
+ if (!supervisor(dc) && asi < 0x80) {
+ gen_exception(dc, TT_PRIV_ACT);
+ type = GET_ASI_EXCP;
+ } else {
+ switch (asi) {
+ case ASI_N: /* Nucleus */
+ case ASI_NL: /* Nucleus LE */
+ mem_idx = MMU_NUCLEUS_IDX;
+ break;
+ case ASI_AIUP: /* As if user primary */
+ case ASI_AIUPL: /* As if user primary LE */
+ mem_idx = MMU_USER_IDX;
+ break;
+ case ASI_AIUS: /* As if user secondary */
+ case ASI_AIUSL: /* As if user secondary LE */
+ mem_idx = MMU_USER_SECONDARY_IDX;
+ break;
+ case ASI_S: /* Secondary */
+ case ASI_SL: /* Secondary LE */
+ if (mem_idx == MMU_USER_IDX) {
+ mem_idx = MMU_USER_SECONDARY_IDX;
+ } else if (mem_idx == MMU_KERNEL_IDX) {
+ mem_idx = MMU_KERNEL_SECONDARY_IDX;
+ }
+ break;
+ case ASI_P: /* Primary */
+ case ASI_PL: /* Primary LE */
+ break;
+ }
+ switch (asi) {
+ case ASI_N:
+ case ASI_NL:
+ case ASI_AIUP:
+ case ASI_AIUPL:
+ case ASI_AIUS:
+ case ASI_AIUSL:
+ case ASI_S:
+ case ASI_SL:
+ case ASI_P:
+ case ASI_PL:
+ type = GET_ASI_DIRECT;
+ break;
+ }
+ /* The little-endian asis all have bit 3 set. */
+ if (asi & 8) {
+ memop ^= MO_BSWAP;
+ }
+ }
#endif
- return (DisasASI){ type, asi };
+ return (DisasASI){ type, asi, mem_idx, memop };
}
static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
int insn, TCGMemOp memop)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, memop);
switch (da.type) {
case GET_ASI_EXCP:
break;
+ case GET_ASI_DIRECT:
+ gen_address_mask(dc, addr);
+ tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
+ break;
default:
{
TCGv_i32 r_asi = tcg_const_i32(da.asi);
@@ -2053,11 +2125,15 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
int insn, TCGMemOp memop)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, memop);
switch (da.type) {
case GET_ASI_EXCP:
break;
+ case GET_ASI_DIRECT:
+ gen_address_mask(dc, addr);
+ tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
+ break;
default:
{
TCGv_i32 r_asi = tcg_const_i32(da.asi);
@@ -2087,7 +2163,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
TCGv addr, int insn)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_TEUL);
switch (da.type) {
case GET_ASI_EXCP:
@@ -2121,7 +2197,7 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
int insn, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_TEUL);
TCGv val1, dst;
TCGv_i32 r_asi;
@@ -2140,7 +2216,7 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_UB);
switch (da.type) {
case GET_ASI_EXCP:
@@ -2175,7 +2251,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
static void gen_ldf_asi(DisasContext *dc, TCGv addr,
int insn, int size, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
switch (da.type) {
case GET_ASI_EXCP:
@@ -2199,7 +2275,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
static void gen_stf_asi(DisasContext *dc, TCGv addr,
int insn, int size, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
switch (da.type) {
case GET_ASI_EXCP:
@@ -2223,7 +2299,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_TEQ);
switch (da.type) {
case GET_ASI_EXCP:
@@ -2245,7 +2321,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_TEQ);
TCGv lo = gen_load_gpr(dc, rd + 1);
switch (da.type) {
@@ -2273,7 +2349,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
int insn, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_TEQ);
TCGv val1 = gen_load_gpr(dc, rd);
TCGv dst = gen_dest_gpr(dc, rd);
TCGv_i32 r_asi;
@@ -2297,9 +2373,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
whereby "rd + 1" elicits "error: array subscript is above array".
Since we have already asserted that rd is even, the semantics
are unchanged. */
- DisasASI da = get_asi(dc, insn);
TCGv lo = gen_dest_gpr(dc, rd | 1);
TCGv_i64 t64 = tcg_temp_new_i64();
+ DisasASI da = get_asi(dc, insn, MO_TEQ);
switch (da.type) {
case GET_ASI_EXCP:
@@ -2329,7 +2405,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
int insn, int rd)
{
- DisasASI da = get_asi(dc, insn);
+ DisasASI da = get_asi(dc, insn, MO_TEQ);
TCGv lo = gen_load_gpr(dc, rd + 1);
TCGv_i64 t64 = tcg_temp_new_i64();
--
2.5.5
next prev parent reply other threads:[~2016-06-02 5:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 5:56 [Qemu-devel] [PATCH v3 00/24] target-sparc improvements Richard Henderson
2016-06-02 5:56 ` [Qemu-devel] [PATCH v3 01/24] target-sparc: Mark more flags for helpers Richard Henderson
2016-06-02 5:56 ` [Qemu-devel] [PATCH v3 02/24] target-sparc: Remove softint as a TCG global Richard Henderson
2016-06-02 5:56 ` [Qemu-devel] [PATCH v3 03/24] target-sparc: Store mmu index in TB flags Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 04/24] target-sparc: Create gen_exception Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 05/24] target-sparc: Unify asi handling between 32 and 64-bit Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 06/24] target-sparc: Store %asi in TB flags Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 07/24] target-sparc: Introduce get_asi Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 08/24] target-sparc: Pass TCGMemOp to gen_ld/st_asi Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 09/24] target-sparc: Import linux/arch/sparc/include/uapi/asm/asi.h Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 10/24] target-sparc: Add UA2011 defines to asi.h Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 11/24] target-sparc: Use defines from asi.h Richard Henderson
2016-06-02 5:57 ` Richard Henderson [this message]
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 13/24] target-sparc: Use QT0 to return results from ldda Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 14/24] target-sparc: Introduce gen_check_align Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 15/24] target-sparc: Directly implement easy ldd/std asis Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 16/24] target-sparc: Fix obvious error in ASI_M_BFILL Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 17/24] target-sparc: Pass TCGMemOp constants to helper_ld/st_asi Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 18/24] target-sparc: Directly implement easy ldf/stf asis Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 19/24] target-sparc: Directly implement block and short " Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 20/24] target-sparc: Remove helper_ldf_asi, helper_stf_asi Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 21/24] target-sparc: Use explicit writes to cpu_fsr Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 22/24] target-sparc: Use cpu_fsr in stfsr Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 23/24] target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptions Richard Henderson
2016-06-02 5:57 ` [Qemu-devel] [PATCH v3 24/24] target-sparc: Elide duplicate updates to fprs Richard Henderson
2016-06-02 12:17 ` [Qemu-devel] [PATCH v3 00/24] target-sparc improvements Artyom Tarasenko
2016-06-24 13:05 ` Artyom Tarasenko
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