All of lore.kernel.org
 help / color / mirror / Atom feed
From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6
Date: Fri,  3 Jun 2016 06:34:34 +0100	[thread overview]
Message-ID: <1464932075-34466-3-git-send-email-arun.siluvery@linux.intel.com> (raw)
In-Reply-To: <1464932075-34466-1-git-send-email-arun.siluvery@linux.intel.com>

Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is
advised to turn it off. But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled. This doesn't affect if the device has all 3
subslices enabled.

Userspace need to know min no. of eus in a pool as it varies based on which
subslice is disabled, this is not yet exported because userspace support is
not available yet. Once the support is available this needs to be exported
using getparam ioctls.

Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Tim Gore <tim.gore@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 10 ++++++++++
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a6c5d87..50aedfd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 
 	if (IS_BROXTON(dev)) {
 #define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
+		/*
+		 * There is a HW issue in 2x6 fused down parts that requires
+		 * Pooled EU to be enabled as a WA. The pool configuration
+		 * changes depending upon which subslice is fused down. This
+		 * doesn't affect if the device has all 3 subslices enabled.
+		 */
+		/* WaEnablePooledEuFor2x6:bxt */
+		info->has_pooled_eu = ((info->subslice_total == 3) ||
+				       (info->subslice_total == 2 &&
+					INTEL_REVID(dev) < BXT_REVID_C0));
 
 		info->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index de78a30..84593c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
-	.has_pooled_eu = 1,
+	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2016-06-03  5:34 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-03  5:34 [PATCH v2 0/3] BXT Pooled EU kernel support and WA patches Arun Siluvery
2016-06-03  5:34 ` [PATCH v2 1/3] drm/i915:bxt: Enable Pooled EU support Arun Siluvery
2016-06-13 17:59   ` Michał Winiarski
2016-06-03  5:34 ` Arun Siluvery [this message]
2016-06-03  9:20   ` [PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6 Mika Kuoppala
2016-06-03 10:14   ` [PATCH v3 " Arun Siluvery
2016-06-03  5:34 ` [PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix Arun Siluvery
2016-06-03  8:06   ` Mika Kuoppala
2016-06-03 10:16   ` [PATCH v3 " Arun Siluvery
2016-06-03  8:23 ` ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches Patchwork
2016-06-03 10:58 ` ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches (rev3) Patchwork
2016-06-06  6:26   ` Arun Siluvery
2016-06-14  9:45     ` Tvrtko Ursulin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1464932075-34466-3-git-send-email-arun.siluvery@linux.intel.com \
    --to=arun.siluvery@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.