From: Dong Aisheng <aisheng.dong@nxp.com> To: <linux-clk@vger.kernel.org> Cc: <linux-kernel@vger.kernel.org>, <sboyd@codeaurora.org>, <mturquette@baylibre.com>, <shawnguo@kernel.org>, <linux-arm-kernel@lists.infradead.org>, <aisheng.dong@nxp.com>, <anson.huang@nxp.com> Subject: [PATCH V3 1/1] clk: imx: refine the powerdown bit of clk-pllv3 Date: Mon, 13 Jun 2016 20:24:52 +0800 [thread overview] Message-ID: <1465820692-20055-1-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1465803434-31507-1-git-send-email-aisheng.dong@nxp.com> The powerdown bit is a bit confused, let's change it to power_bit to relfect both powerdown and powerup case according to different plls. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- Changes from v2: Sorry for sending the patch too quickly. There's a rebase error in V2, fixed it. --- drivers/clk/imx/clk-pllv3.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index eea2b1b3791e..19f9b622981a 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -29,8 +29,8 @@ * struct clk_pllv3 - IMX PLL clock version 3 * @clk_hw: clock source * @base: base address of PLL registers - * @powerup_set: set POWER bit to power up the PLL - * @powerdown: pll powerdown offset bit + * @power_bit: pll power bit mask + * @powerup_set: set power_bit to power up the PLL * @div_mask: mask of divider bits * @div_shift: shift of divider bits * @@ -40,8 +40,8 @@ struct clk_pllv3 { struct clk_hw hw; void __iomem *base; + u32 power_bit; bool powerup_set; - u32 powerdown; u32 div_mask; u32 div_shift; unsigned long ref_clock; @@ -52,7 +52,7 @@ struct clk_pllv3 { static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) { unsigned long timeout = jiffies + msecs_to_jiffies(10); - u32 val = readl_relaxed(pll->base) & pll->powerdown; + u32 val = readl_relaxed(pll->base) & pll->power_bit; /* No need to wait for lock when pll is not powered up */ if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) @@ -77,9 +77,9 @@ static int clk_pllv3_prepare(struct clk_hw *hw) val = readl_relaxed(pll->base); if (pll->powerup_set) - val |= pll->powerdown; + val |= pll->power_bit; else - val &= ~pll->powerdown; + val &= ~pll->power_bit; writel_relaxed(val, pll->base); return clk_pllv3_wait_lock(pll); @@ -92,9 +92,9 @@ static void clk_pllv3_unprepare(struct clk_hw *hw) val = readl_relaxed(pll->base); if (pll->powerup_set) - val &= ~pll->powerdown; + val &= ~pll->power_bit; else - val |= pll->powerdown; + val |= pll->power_bit; writel_relaxed(val, pll->base); } @@ -316,7 +316,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, if (!pll) return ERR_PTR(-ENOMEM); - pll->powerdown = BM_PLL_POWER; + pll->power_bit = BM_PLL_POWER; switch (type) { case IMX_PLLV3_SYS: @@ -332,7 +332,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, ops = &clk_pllv3_av_ops; break; case IMX_PLLV3_ENET_IMX7: - pll->powerdown = IMX7_ENET_PLL_POWER; + pll->power_bit = IMX7_ENET_PLL_POWER; pll->ref_clock = 1000000000; ops = &clk_pllv3_enet_ops; break; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: aisheng.dong@nxp.com (Dong Aisheng) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V3 1/1] clk: imx: refine the powerdown bit of clk-pllv3 Date: Mon, 13 Jun 2016 20:24:52 +0800 [thread overview] Message-ID: <1465820692-20055-1-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1465803434-31507-1-git-send-email-aisheng.dong@nxp.com> The powerdown bit is a bit confused, let's change it to power_bit to relfect both powerdown and powerup case according to different plls. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- Changes from v2: Sorry for sending the patch too quickly. There's a rebase error in V2, fixed it. --- drivers/clk/imx/clk-pllv3.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index eea2b1b3791e..19f9b622981a 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -29,8 +29,8 @@ * struct clk_pllv3 - IMX PLL clock version 3 * @clk_hw: clock source * @base: base address of PLL registers - * @powerup_set: set POWER bit to power up the PLL - * @powerdown: pll powerdown offset bit + * @power_bit: pll power bit mask + * @powerup_set: set power_bit to power up the PLL * @div_mask: mask of divider bits * @div_shift: shift of divider bits * @@ -40,8 +40,8 @@ struct clk_pllv3 { struct clk_hw hw; void __iomem *base; + u32 power_bit; bool powerup_set; - u32 powerdown; u32 div_mask; u32 div_shift; unsigned long ref_clock; @@ -52,7 +52,7 @@ struct clk_pllv3 { static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) { unsigned long timeout = jiffies + msecs_to_jiffies(10); - u32 val = readl_relaxed(pll->base) & pll->powerdown; + u32 val = readl_relaxed(pll->base) & pll->power_bit; /* No need to wait for lock when pll is not powered up */ if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) @@ -77,9 +77,9 @@ static int clk_pllv3_prepare(struct clk_hw *hw) val = readl_relaxed(pll->base); if (pll->powerup_set) - val |= pll->powerdown; + val |= pll->power_bit; else - val &= ~pll->powerdown; + val &= ~pll->power_bit; writel_relaxed(val, pll->base); return clk_pllv3_wait_lock(pll); @@ -92,9 +92,9 @@ static void clk_pllv3_unprepare(struct clk_hw *hw) val = readl_relaxed(pll->base); if (pll->powerup_set) - val &= ~pll->powerdown; + val &= ~pll->power_bit; else - val |= pll->powerdown; + val |= pll->power_bit; writel_relaxed(val, pll->base); } @@ -316,7 +316,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, if (!pll) return ERR_PTR(-ENOMEM); - pll->powerdown = BM_PLL_POWER; + pll->power_bit = BM_PLL_POWER; switch (type) { case IMX_PLLV3_SYS: @@ -332,7 +332,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, ops = &clk_pllv3_av_ops; break; case IMX_PLLV3_ENET_IMX7: - pll->powerdown = IMX7_ENET_PLL_POWER; + pll->power_bit = IMX7_ENET_PLL_POWER; pll->ref_clock = 1000000000; ops = &clk_pllv3_enet_ops; break; -- 1.9.1
next prev parent reply other threads:[~2016-06-13 12:31 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-08 14:33 [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 02/11] clk: imx: correct AV PLL rate formula Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:30 ` Shawn Guo 2016-06-12 11:30 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 03/11] clk: imx7d: correct dram root clk parent select Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:31 ` Shawn Guo 2016-06-12 11:31 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 04/11] clk: imx: correct dram pll type Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:33 ` Shawn Guo 2016-06-12 11:33 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3 Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-09 7:43 ` Lothar Waßmann 2016-06-09 7:43 ` Lothar Waßmann 2016-06-09 7:43 ` Lothar Waßmann 2016-06-12 11:56 ` Dong Aisheng 2016-06-12 11:56 ` Dong Aisheng 2016-06-12 11:36 ` Shawn Guo 2016-06-12 11:36 ` Shawn Guo 2016-06-12 11:51 ` Dong Aisheng 2016-06-12 11:51 ` Dong Aisheng 2016-06-12 12:13 ` Dong Aisheng 2016-06-12 12:13 ` Dong Aisheng 2016-06-12 13:29 ` Shawn Guo 2016-06-12 13:29 ` Shawn Guo 2016-06-12 14:51 ` Dong Aisheng 2016-06-12 14:51 ` Dong Aisheng 2016-06-12 14:51 ` Dong Aisheng 2016-06-13 7:37 ` [PATCH V2 1/1] clk: imx: refine the powerdown " Dong Aisheng 2016-06-13 7:37 ` Dong Aisheng 2016-06-13 11:42 ` kbuild test robot 2016-06-13 11:42 ` kbuild test robot 2016-06-13 12:24 ` Dong Aisheng [this message] 2016-06-13 12:24 ` [PATCH V3 " Dong Aisheng 2016-06-16 1:05 ` Shawn Guo 2016-06-16 1:05 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 06/11] clk: imx6ul: fix gpt2 clock names Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:41 ` Shawn Guo 2016-06-12 11:41 ` Shawn Guo 2016-06-12 11:52 ` Dong Aisheng 2016-06-12 11:52 ` Dong Aisheng 2016-06-13 7:38 ` [PATCH V2 1/1] " Dong Aisheng 2016-06-13 7:38 ` Dong Aisheng 2016-06-16 1:06 ` Shawn Guo 2016-06-16 1:06 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 07/11] clk: imx6ul: fix pll clock parents Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 11:43 ` Shawn Guo 2016-06-12 11:43 ` Shawn Guo 2016-06-12 11:52 ` Dong Aisheng 2016-06-12 11:52 ` Dong Aisheng 2016-06-12 12:19 ` Dong Aisheng 2016-06-12 12:19 ` Dong Aisheng 2016-06-12 13:22 ` Shawn Guo 2016-06-12 13:22 ` Shawn Guo 2016-06-08 14:33 ` [PATCH 08/11] clk: imx6q: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 09/11] clk: imx6sx: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 10/11] clk: imx6sl: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-08 14:33 ` [PATCH 11/11] clk: imx7d: " Dong Aisheng 2016-06-08 14:33 ` Dong Aisheng 2016-06-12 14:56 ` [PATCH 01/11] clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit Dong Aisheng 2016-06-12 14:56 ` Dong Aisheng 2016-06-12 14:56 ` Dong Aisheng 2016-06-13 2:54 ` Shawn Guo 2016-06-13 2:54 ` Shawn Guo 2016-06-13 2:54 ` Shawn Guo
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