From: Xing Zheng <zhengxing@rock-chips.com> To: heiko@sntech.de Cc: dianders@chromium.org, zhangqing@rock-chips.com, huangtao@rock-chips.com, briannorris@chromium.org, zyw@rock-chips.com, Xing Zheng <zhengxing@rock-chips.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX Date: Thu, 30 Jun 2016 10:18:59 +0800 [thread overview] Message-ID: <1467253139-21112-1-git-send-email-zhengxing@rock-chips.com> (raw) The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it. Reported-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- drivers/clk/rockchip/clk-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index b6742fa..78e51cb 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, - RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(10), 6, GFLAGS), /* i2s */ COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, -- 1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: zhengxing@rock-chips.com (Xing Zheng) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX Date: Thu, 30 Jun 2016 10:18:59 +0800 [thread overview] Message-ID: <1467253139-21112-1-git-send-email-zhengxing@rock-chips.com> (raw) The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it. Reported-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> --- drivers/clk/rockchip/clk-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index b6742fa..78e51cb 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, - RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(10), 6, GFLAGS), /* i2s */ COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, -- 1.7.9.5
next reply other threads:[~2016-06-30 2:19 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-30 2:18 Xing Zheng [this message] 2016-06-30 2:18 ` [PATCH] clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX Xing Zheng 2016-07-01 8:31 ` Heiko Stuebner 2016-07-01 8:31 ` Heiko Stuebner 2016-07-01 8:31 ` Heiko Stuebner
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