From: William Wu <william.wu@rock-chips.com> To: gregkh@linuxfoundation.org, balbi@kernel.org, heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, briannorris@google.com, dianders@google.com, kever.yang@rock-chips.com, huangtao@rock-chips.com, frank.wang@rock-chips.com, eddie.cai@rock-chips.com, John.Youn@synopsys.com, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, sergei.shtylyov@cogentembedded.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, William Wu <william.wu@rock-chips.com> Subject: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk Date: Thu, 30 Jun 2016 19:12:55 +0800 [thread overview] Message-ID: <1467285176-25222-5-git-send-email-william.wu@rock-chips.com> (raw) In-Reply-To: <1467285176-25222-1-git-send-email-william.wu@rock-chips.com> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu <william.wu@rock-chips.com> --- Changes in v5: - None Changes in v4: - rebase on top of balbi testing/next, remove pdata (balbi) Changes in v3: - None Changes in v2: - None Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ drivers/usb/dwc3/core.c | 5 +++++ drivers/usb/dwc3/core.h | 3 +++ 3 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 34d13a5..bd5bef0 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -42,6 +42,8 @@ Optional properties: - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 PHY doesn't provide a free-running PHY clock. + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power + from P0 to P1/P2/P3 without delay. - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. Value 0 select 8-bit diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index e880686..320a50f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -449,6 +449,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u3_susphy_quirk) reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; + if (dwc->dis_del_phy_power_chg_quirk) + reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); @@ -943,6 +946,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,dis_rxdet_inp3_quirk"); dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, "snps,dis_u2_freeclk_exists_quirk"); + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, + "snps,dis_del_phy_power_chg_quirk"); dwc->phyif_utmi_quirk = device_property_read_bool(dev, "snps,phyif_utmi_quirk"); device_property_read_u8(dev, "snps,phyif_utmi", diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index cf6696c..55e136d 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -809,6 +809,8 @@ struct dwc3_scratchpad_array { * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists * in GUSB2PHYCFG, specify that USB2 PHY doesn't * provide a free-running PHY clock. + * @dis_del_phy_power_chg_quirk: set if we disable delay phy power + * change quirk. * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk * @phyif_utmi: UTMI+ PHY interface value * 0 - 8 bits @@ -957,6 +959,7 @@ struct dwc3 { unsigned dis_enblslpm_quirk:1; unsigned dis_rxdet_inp3_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; + unsigned dis_del_phy_power_chg_quirk:1; unsigned phyif_utmi_quirk:1; unsigned phyif_utmi:1; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org, dianders-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, eddie.cai-TNX95d0MmH7DzftRWevZcw@public.gmane.org, William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, briannorris-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, John.Youn-HKixBCOQz3hWk0Htik3J/w@public.gmane.org Subject: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk Date: Thu, 30 Jun 2016 19:12:55 +0800 [thread overview] Message-ID: <1467285176-25222-5-git-send-email-william.wu@rock-chips.com> (raw) In-Reply-To: <1467285176-25222-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v5: - None Changes in v4: - rebase on top of balbi testing/next, remove pdata (balbi) Changes in v3: - None Changes in v2: - None Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ drivers/usb/dwc3/core.c | 5 +++++ drivers/usb/dwc3/core.h | 3 +++ 3 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 34d13a5..bd5bef0 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -42,6 +42,8 @@ Optional properties: - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 PHY doesn't provide a free-running PHY clock. + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power + from P0 to P1/P2/P3 without delay. - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. Value 0 select 8-bit diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index e880686..320a50f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -449,6 +449,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u3_susphy_quirk) reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; + if (dwc->dis_del_phy_power_chg_quirk) + reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); @@ -943,6 +946,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,dis_rxdet_inp3_quirk"); dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, "snps,dis_u2_freeclk_exists_quirk"); + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, + "snps,dis_del_phy_power_chg_quirk"); dwc->phyif_utmi_quirk = device_property_read_bool(dev, "snps,phyif_utmi_quirk"); device_property_read_u8(dev, "snps,phyif_utmi", diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index cf6696c..55e136d 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -809,6 +809,8 @@ struct dwc3_scratchpad_array { * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists * in GUSB2PHYCFG, specify that USB2 PHY doesn't * provide a free-running PHY clock. + * @dis_del_phy_power_chg_quirk: set if we disable delay phy power + * change quirk. * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk * @phyif_utmi: UTMI+ PHY interface value * 0 - 8 bits @@ -957,6 +959,7 @@ struct dwc3 { unsigned dis_enblslpm_quirk:1; unsigned dis_rxdet_inp3_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; + unsigned dis_del_phy_power_chg_quirk:1; unsigned phyif_utmi_quirk:1; unsigned phyif_utmi:1; -- 1.9.1
next prev parent reply other threads:[~2016-06-30 11:14 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-30 11:12 [PATCH v5 0/5] support rockchip dwc3 driver William Wu 2016-06-30 11:12 ` William Wu 2016-06-30 11:12 ` [PATCH v5 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399 William Wu 2016-06-30 11:12 ` William Wu 2016-06-30 11:12 ` [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu 2016-06-30 11:12 ` William Wu 2016-07-01 2:32 ` Rob Herring 2016-07-01 2:49 ` [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk[Involving remittance information, please pay attention to the safety of property] William Wu 2016-07-01 2:49 ` William Wu 2016-06-30 11:12 ` [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk William Wu 2016-07-01 2:35 ` Rob Herring 2016-07-01 2:35 ` Rob Herring 2016-07-01 3:45 ` [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk[Involving remittance information, please pay attention to the safety of property] William Wu 2016-07-01 3:53 ` William Wu 2016-06-30 11:12 ` William Wu [this message] 2016-06-30 11:12 ` [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu 2016-07-01 2:38 ` Rob Herring 2016-07-01 2:38 ` Rob Herring 2016-07-01 2:51 ` [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk[Involving remittance information, please pay attention to the safety of property] William Wu 2016-06-30 11:16 ` [PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation William Wu 2016-06-30 12:15 ` Heiko Stuebner 2016-07-01 1:20 ` William Wu 2016-07-01 1:20 ` William Wu
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