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From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <rth@twiddle.net>,
	qemu-devel@nongnu.org, Haozhong Zhang <haozhong.zhang@intel.com>
Subject: [Qemu-devel] [PULL 15/16] target-i386: Publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg
Date: Thu,  7 Jul 2016 16:59:21 -0300	[thread overview]
Message-ID: <1467921562-11796-16-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1467921562-11796-1-git-send-email-ehabkost@redhat.com>

From: Haozhong Zhang <haozhong.zhang@intel.com>

It's a prerequisite that certain bits of MSR_IA32_FEATURE_CONTROL should
be set before some features (e.g. VMX and LMCE) can be used, which is
usually done by the firmware. This patch adds a fw_cfg file
"etc/msr_feature_control" which contains the advised value of
MSR_IA32_FEATURE_CONTROL and can be used by guest firmware (e.g. SeaBIOS).

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 hw/i386/pc.c      | 29 +++++++++++++++++++++++++++++
 target-i386/cpu.h |  4 ++++
 2 files changed, 33 insertions(+)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index d0df3c1..f56e225 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1166,6 +1166,34 @@ void pc_cpus_init(PCMachineState *pcms)
     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 }
 
+static void pc_build_feature_control_file(PCMachineState *pcms)
+{
+    X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu);
+    CPUX86State *env = &cpu->env;
+    uint32_t unused, ecx, edx;
+    uint64_t feature_control_bits = 0;
+    uint64_t *val;
+
+    cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
+    if (ecx & CPUID_EXT_VMX) {
+        feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
+    }
+
+    if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
+        (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
+        (env->mcg_cap & MCG_LMCE_P)) {
+        feature_control_bits |= FEATURE_CONTROL_LMCE;
+    }
+
+    if (!feature_control_bits) {
+        return;
+    }
+
+    val = g_malloc(sizeof(*val));
+    *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
+    fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
+}
+
 static
 void pc_machine_done(Notifier *notifier, void *data)
 {
@@ -1193,6 +1221,7 @@ void pc_machine_done(Notifier *notifier, void *data)
     acpi_setup();
     if (pcms->fw_cfg) {
         pc_build_smbios(pcms->fw_cfg);
+        pc_build_feature_control_file(pcms);
     }
 }
 
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 54c3fd6..5c7a279 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -332,6 +332,10 @@
 #define MSR_TSC_ADJUST                  0x0000003b
 #define MSR_IA32_TSCDEADLINE            0x6e0
 
+#define FEATURE_CONTROL_LOCKED                    (1<<0)
+#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
+#define FEATURE_CONTROL_LMCE                      (1<<20)
+
 #define MSR_P6_PERFCTR0                 0xc1
 
 #define MSR_IA32_SMBASE                 0x9e
-- 
2.5.5

  parent reply	other threads:[~2016-07-07 20:00 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-07 19:59 [Qemu-devel] [PULL 00/16] x86 and machine queue, 2016-07-07 Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 01/16] qdev: Don't stop applying globals on first error Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 02/16] qdev: Eliminate qemu_add_globals() function Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 03/16] qdev: GlobalProperty.errp field Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 04/16] machine: Add machine_register_compat_props() function Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 05/16] vl: Set errp to &error_abort on machine compat_props Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 06/16] target-sparc: Use sparc_cpu_parse_features() directly Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 07/16] target-i386: TCG can support CPUID.07H:EBX.erms Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 08/16] target-i386: Avoid using locals outside their scope Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 09/16] cpu: Use CPUClass->parse_features() as convertor to global properties Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 10/16] arm: virt: Parse cpu_model only once Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 11/16] pc: Parse CPU features " Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 12/16] target-i386: Show host and VM TSC frequencies on mismatch Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 13/16] target-i386: Report hyperv feature words through qom Eduardo Habkost
2016-07-07 19:59 ` [Qemu-devel] [PULL 14/16] target-i386: kvm: Add basic Intel LMCE support Eduardo Habkost
2016-07-07 19:59 ` Eduardo Habkost [this message]
2016-07-07 19:59 ` [Qemu-devel] [PULL 16/16] target-i386: Enable LMCE for '-cpu host' if supported by host Eduardo Habkost
2016-07-11 14:59 ` [Qemu-devel] [PULL 00/16] x86 and machine queue, 2016-07-07 Peter Maydell

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