From: Chen-Yu Tsai <wens@csie.org> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Maxime Ripard <maxime.ripard@free-electrons.com> Cc: dev@linux-sunxi.org, Chen-Yu Tsai <wens@csie.org>, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/9] clk: sunxi-ng: mux: Add support for mux tables Date: Tue, 26 Jul 2016 15:04:26 +0800 [thread overview] Message-ID: <1469516671-19377-5-git-send-email-wens@csie.org> (raw) In-Reply-To: <1469516671-19377-1-git-send-email-wens@csie.org> Some clock muxes have holes, i.e. invalid or unconnected inputs, between parent mux values. Add support for specifying a mux table to map clock parents to mux values. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu_mux.c | 12 ++++++++++++ drivers/clk/sunxi-ng/ccu_mux.h | 12 ++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 1329b9ab481e..68b32f168a74 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common, parent = reg >> cm->shift; parent &= (1 << cm->width) - 1; + if (cm->table) { + int num_parents = clk_hw_get_num_parents(&common->hw); + int i; + + for (i = 0; i < num_parents; i++) + if (cm->table[i] == parent) + return i; + } + return parent; } @@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, unsigned long flags; u32 reg; + if (cm->table) + index = cm->table[index]; + spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index d35ce5e93840..f0078de78712 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -6,8 +6,9 @@ #include "ccu_common.h" struct ccu_mux_internal { - u8 shift; - u8 width; + u8 shift; + u8 width; + const u8 *table; struct { u8 index; @@ -21,6 +22,13 @@ struct ccu_mux_internal { } variable_prediv; }; +#define SUNXI_CLK_MUX_TABLE(_shift, _width, _table) \ + { \ + .shift = _shift, \ + .width = _width, \ + .table = _table, \ + } + #define SUNXI_CLK_MUX(_shift, _width) \ { \ .shift = _shift, \ -- 2.8.1
WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] clk: sunxi-ng: mux: Add support for mux tables Date: Tue, 26 Jul 2016 15:04:26 +0800 [thread overview] Message-ID: <1469516671-19377-5-git-send-email-wens@csie.org> (raw) In-Reply-To: <1469516671-19377-1-git-send-email-wens@csie.org> Some clock muxes have holes, i.e. invalid or unconnected inputs, between parent mux values. Add support for specifying a mux table to map clock parents to mux values. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu_mux.c | 12 ++++++++++++ drivers/clk/sunxi-ng/ccu_mux.h | 12 ++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 1329b9ab481e..68b32f168a74 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common, parent = reg >> cm->shift; parent &= (1 << cm->width) - 1; + if (cm->table) { + int num_parents = clk_hw_get_num_parents(&common->hw); + int i; + + for (i = 0; i < num_parents; i++) + if (cm->table[i] == parent) + return i; + } + return parent; } @@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, unsigned long flags; u32 reg; + if (cm->table) + index = cm->table[index]; + spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index d35ce5e93840..f0078de78712 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -6,8 +6,9 @@ #include "ccu_common.h" struct ccu_mux_internal { - u8 shift; - u8 width; + u8 shift; + u8 width; + const u8 *table; struct { u8 index; @@ -21,6 +22,13 @@ struct ccu_mux_internal { } variable_prediv; }; +#define SUNXI_CLK_MUX_TABLE(_shift, _width, _table) \ + { \ + .shift = _shift, \ + .width = _width, \ + .table = _table, \ + } + #define SUNXI_CLK_MUX(_shift, _width) \ { \ .shift = _shift, \ -- 2.8.1
next prev parent reply other threads:[~2016-07-26 7:04 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-07-26 7:04 [PATCH 0/9] clk: sunxi-ng: Support A31/A31s CCU Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` [PATCH resend 1/9] clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 8:56 ` Maxime Ripard 2016-07-26 8:56 ` Maxime Ripard 2016-07-26 8:56 ` Maxime Ripard 2016-07-26 7:04 ` [PATCH 2/9] clk: sunxi-ng: nk: Make ccu_nk_find_best static Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 8:57 ` Maxime Ripard 2016-07-26 8:57 ` Maxime Ripard 2016-07-26 8:57 ` Maxime Ripard 2016-07-26 7:04 ` [PATCH 3/9] clk: sunxi-ng: mux: Increase fixed pre-divider div size Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-27 6:43 ` Maxime Ripard 2016-07-27 6:43 ` Maxime Ripard 2016-07-27 6:43 ` Maxime Ripard 2016-07-26 7:04 ` Chen-Yu Tsai [this message] 2016-07-26 7:04 ` [PATCH 4/9] clk: sunxi-ng: mux: Add support for mux tables Chen-Yu Tsai 2016-07-26 17:43 ` Jean-Francois Moine 2016-07-26 17:43 ` Jean-Francois Moine 2016-07-26 17:43 ` Jean-Francois Moine 2016-07-27 6:59 ` Maxime Ripard 2016-07-27 6:59 ` Maxime Ripard 2016-07-27 7:18 ` Jean-Francois Moine 2016-07-27 7:18 ` Jean-Francois Moine 2016-07-27 7:18 ` Jean-Francois Moine 2016-07-27 7:30 ` Chen-Yu Tsai 2016-07-27 7:30 ` Chen-Yu Tsai 2016-07-27 7:40 ` Maxime Ripard 2016-07-27 7:40 ` Maxime Ripard 2016-07-27 7:40 ` Maxime Ripard 2016-07-27 8:36 ` Jean-Francois Moine 2016-07-27 8:36 ` Jean-Francois Moine 2016-07-27 8:36 ` Jean-Francois Moine 2016-07-28 13:28 ` Maxime Ripard 2016-07-28 13:28 ` Maxime Ripard 2016-07-28 13:28 ` Maxime Ripard 2016-07-28 14:23 ` Jean-Francois Moine 2016-07-28 14:23 ` Jean-Francois Moine 2016-07-28 14:23 ` Jean-Francois Moine 2016-07-28 14:23 ` Jean-Francois Moine 2016-07-27 6:48 ` Maxime Ripard 2016-07-27 6:48 ` Maxime Ripard 2016-07-27 6:48 ` Maxime Ripard 2016-07-26 7:04 ` [PATCH 5/9] clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-27 7:26 ` Maxime Ripard 2016-07-27 7:26 ` Maxime Ripard 2016-07-27 7:26 ` Maxime Ripard 2016-07-27 8:38 ` Jean-Francois Moine 2016-07-27 8:38 ` Jean-Francois Moine 2016-07-27 8:38 ` Jean-Francois Moine 2016-07-26 7:04 ` [PATCH 6/9] clk: sunxi-ng: nkm: Add mux to support " Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-27 7:27 ` Maxime Ripard 2016-07-27 7:27 ` Maxime Ripard 2016-07-27 7:27 ` Maxime Ripard 2016-07-26 7:04 ` [PATCH 7/9] clk: sunxi-ng: mux: Add clk notifier functions Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-27 7:30 ` Maxime Ripard 2016-07-27 7:30 ` Maxime Ripard 2016-07-27 7:30 ` Maxime Ripard 2016-07-27 7:32 ` Chen-Yu Tsai 2016-07-27 7:32 ` Chen-Yu Tsai 2016-07-27 7:43 ` Maxime Ripard 2016-07-27 7:43 ` Maxime Ripard 2016-07-27 7:43 ` Maxime Ripard 2016-07-26 7:04 ` [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 8:30 ` Jean-Francois Moine 2016-07-26 8:30 ` Jean-Francois Moine 2016-07-26 8:30 ` Jean-Francois Moine 2016-07-27 14:59 ` Rob Herring 2016-07-27 14:59 ` Rob Herring 2016-07-28 13:31 ` Maxime Ripard 2016-07-28 13:31 ` Maxime Ripard 2016-07-28 13:31 ` Maxime Ripard 2016-07-26 7:04 ` [PATCH 9/9] ARM: dts: sun6i: switch A31/A31s to new CCU clock bindings Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai 2016-07-26 7:04 ` Chen-Yu Tsai
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