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From: Caesar Wang <wxt@rock-chips.com>
To: jic23@kernel.org, heiko@sntech.de
Cc: devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org,
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org,
	john@metanate.com, dianders@chromium.org, linux@roeck-us.net,
	Caesar Wang <wxt@rock-chips.com>
Subject: [PATCH v2 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs
Date: Tue, 26 Jul 2016 20:13:15 +0800	[thread overview]
Message-ID: <1469535195-5227-4-git-send-email-wxt@rock-chips.com> (raw)
In-Reply-To: <1469535195-5227-1-git-send-email-wxt@rock-chips.com>

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v2: None

 arch/arm/boot/dts/rk3066a.dtsi | 2 ++
 arch/arm/boot/dts/rk3288.dtsi  | 2 ++
 arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index c0ba86c..0d0dae3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -197,6 +197,8 @@
 		clock-names = "saradc", "apb_pclk";
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		#io-channel-cells = <1>;
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cd33f01..91c4b3c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -279,6 +279,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 99bbcc2..e2cd683 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -399,6 +399,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

WARNING: multiple messages have this Message-ID (diff)
From: wxt@rock-chips.com (Caesar Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs
Date: Tue, 26 Jul 2016 20:13:15 +0800	[thread overview]
Message-ID: <1469535195-5227-4-git-send-email-wxt@rock-chips.com> (raw)
In-Reply-To: <1469535195-5227-1-git-send-email-wxt@rock-chips.com>

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v2: None

 arch/arm/boot/dts/rk3066a.dtsi | 2 ++
 arch/arm/boot/dts/rk3288.dtsi  | 2 ++
 arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index c0ba86c..0d0dae3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -197,6 +197,8 @@
 		clock-names = "saradc", "apb_pclk";
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		#io-channel-cells = <1>;
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cd33f01..91c4b3c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -279,6 +279,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 99bbcc2..e2cd683 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -399,6 +399,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

  parent reply	other threads:[~2016-07-26 12:13 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-26 12:13 [PATCH v2 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it Caesar Wang
2016-07-26 12:13 ` Caesar Wang
2016-07-26 12:13 ` Caesar Wang
2016-07-26 12:13 ` [PATCH v2 2/4] arm64: dts: rockchip: add the saradc for rk3399 Caesar Wang
2016-07-26 12:13   ` Caesar Wang
2016-07-27  4:07   ` Doug Anderson
2016-07-27  4:07     ` Doug Anderson
2016-07-27  4:07     ` Doug Anderson
2016-07-26 12:13 ` [PATCH v2 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs Caesar Wang
2016-07-26 12:13   ` Caesar Wang
2016-07-26 12:13 ` Caesar Wang [this message]
2016-07-26 12:13   ` [PATCH v2 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs Caesar Wang
2016-07-26 13:39 ` [PATCH v2 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it Guenter Roeck
2016-07-26 13:39   ` Guenter Roeck
2016-07-26 13:39   ` Guenter Roeck
2016-07-26 14:47   ` Caesar Wang
2016-07-26 14:47     ` Caesar Wang
2016-07-26 14:47     ` Caesar Wang
2016-07-26 17:00     ` Guenter Roeck
2016-07-26 17:00       ` Guenter Roeck
2016-07-26 17:00       ` Guenter Roeck
2016-07-27  0:42       ` Caesar Wang
2016-07-27  0:42         ` Caesar Wang
2016-07-27  0:42         ` Caesar Wang
2016-07-27  2:00         ` Guenter Roeck
2016-07-27  2:00           ` Guenter Roeck
2016-07-27  2:00           ` Guenter Roeck
2016-07-27  2:11           ` Caesar Wang
2016-07-27  2:11             ` Caesar Wang
2016-07-27  2:11             ` Caesar Wang
2016-07-26 22:41 ` Guenter Roeck
2016-07-26 22:41   ` Guenter Roeck
2016-07-26 22:41   ` Guenter Roeck
2016-07-27 15:12 ` Rob Herring
2016-07-27 15:12   ` Rob Herring

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