From: Lin Huang <hl@rock-chips.com> To: heiko@sntech.de, cw00.choi@samsung.com Cc: tixy@linaro.org, dbasehore@chromium.org, airlied@linux.ie, mturquette@baylibre.com, typ@rock-chips.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, linux-arm-kernel@lists.infradead.org, mark.yao@rock-chips.com, Lin Huang <hl@rock-chips.com> Subject: [PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support Date: Fri, 29 Jul 2016 15:56:58 +0800 [thread overview] Message-ID: <1469779021-10426-5-git-send-email-hl@rock-chips.com> (raw) In-Reply-To: <1469779021-10426-1-git-send-email-hl@rock-chips.com> add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future. Signed-off-by: Lin Huang <hl@rock-chips.com> --- Changes in v4: - None Changes in v3: - None Changes in v2: - remove clk_ddrc_dpll_src from critical clock list Changes in v1: - remove ddrc source CLK_IGNORE_UNUSED flag - move clk_ddrc and clk_ddrc_dpll_src to critical drivers/clk/rockchip/clk-rk3399.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index d4a1cf0..b7b42d9 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -118,6 +118,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", + "clk_ddrc_bpll_src", + "clk_ddrc_dpll_src", + "clk_ddrc_gpll_src" }; PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS), + + /* ddrc */ + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), + 0, GFLAGS), + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), + 1, GFLAGS), + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), + 2, GFLAGS), + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), + 3, GFLAGS), + COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p, 0, + RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS), }; static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { @@ -1487,6 +1503,9 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { "gpll_hclk_perilp1_src", "gpll_aclk_perilp0_src", "gpll_aclk_perihp_src", + + /* ddrc */ + "clk_ddrc" }; static const char *const rk3399_pmucru_critical_clocks[] __initconst = { -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: hl@rock-chips.com (Lin Huang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support Date: Fri, 29 Jul 2016 15:56:58 +0800 [thread overview] Message-ID: <1469779021-10426-5-git-send-email-hl@rock-chips.com> (raw) In-Reply-To: <1469779021-10426-1-git-send-email-hl@rock-chips.com> add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future. Signed-off-by: Lin Huang <hl@rock-chips.com> --- Changes in v4: - None Changes in v3: - None Changes in v2: - remove clk_ddrc_dpll_src from critical clock list Changes in v1: - remove ddrc source CLK_IGNORE_UNUSED flag - move clk_ddrc and clk_ddrc_dpll_src to critical drivers/clk/rockchip/clk-rk3399.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index d4a1cf0..b7b42d9 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -118,6 +118,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", + "clk_ddrc_bpll_src", + "clk_ddrc_dpll_src", + "clk_ddrc_gpll_src" }; PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS), + + /* ddrc */ + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), + 0, GFLAGS), + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), + 1, GFLAGS), + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), + 2, GFLAGS), + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), + 3, GFLAGS), + COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p, 0, + RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS), }; static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { @@ -1487,6 +1503,9 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { "gpll_hclk_perilp1_src", "gpll_aclk_perilp0_src", "gpll_aclk_perihp_src", + + /* ddrc */ + "clk_ddrc" }; static const char *const rk3399_pmucru_critical_clocks[] __initconst = { -- 1.9.1
next prev parent reply other threads:[~2016-07-29 7:57 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20160729075805epcas1p2fa2fab53fc8cdfdf42f53e99a0a72e6a@epcas1p2.samsung.com> 2016-07-29 7:56 ` [PATCH v4 0/7] rk3399 support ddr frequency scaling Lin Huang 2016-07-29 7:56 ` Lin Huang 2016-07-29 7:56 ` [PATCH v4 1/7] clk: rockchip: add clock flag parameter when register pll Lin Huang 2016-07-29 7:56 ` Lin Huang 2016-08-04 22:37 ` Heiko Stuebner 2016-08-04 22:37 ` Heiko Stuebner 2016-08-05 8:50 ` hl 2016-08-05 8:50 ` hl 2016-08-05 8:55 ` Heiko Stübner 2016-08-05 8:55 ` Heiko Stübner 2016-08-05 8:55 ` Heiko Stübner 2016-07-29 7:56 ` [PATCH v4 2/7] clk: rockchip: add new clock-type for the ddrclk Lin Huang 2016-07-29 7:56 ` Lin Huang 2016-08-04 20:23 ` Heiko Stübner 2016-08-04 20:23 ` Heiko Stübner 2016-08-04 22:42 ` Heiko Stuebner 2016-08-04 22:42 ` Heiko Stuebner 2016-07-29 7:56 ` [PATCH v4 3/7] clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc Lin Huang 2016-07-29 7:56 ` Lin Huang 2016-08-04 22:40 ` Heiko Stuebner 2016-08-04 22:40 ` Heiko Stuebner 2016-08-04 22:40 ` Heiko Stuebner 2016-07-29 7:56 ` Lin Huang [this message] 2016-07-29 7:56 ` [PATCH v4 4/7] clk: rockchip: rk3399: add ddrc clock support Lin Huang 2016-07-29 7:56 ` [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Lin Huang 2016-07-29 7:56 ` Lin Huang 2016-08-01 7:41 ` Chanwoo Choi 2016-08-01 7:41 ` Chanwoo Choi 2016-08-01 7:41 ` Chanwoo Choi 2016-08-01 8:08 ` Chanwoo Choi 2016-08-01 8:08 ` Chanwoo Choi 2016-08-01 8:08 ` Chanwoo Choi 2016-08-01 8:27 ` hl 2016-08-01 8:27 ` hl 2016-08-01 10:31 ` Chanwoo Choi 2016-08-01 10:31 ` Chanwoo Choi 2016-07-29 7:57 ` [PATCH v4 6/7] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc Lin Huang 2016-07-29 7:57 ` Lin Huang 2016-08-01 10:28 ` Chanwoo Choi 2016-08-01 10:28 ` Chanwoo Choi 2016-08-01 10:28 ` Chanwoo Choi 2016-08-02 1:03 ` hl 2016-08-02 1:03 ` hl 2016-08-02 1:03 ` hl 2016-08-02 4:21 ` Chanwoo Choi 2016-08-02 4:21 ` Chanwoo Choi 2016-08-03 7:38 ` hl 2016-08-03 7:38 ` hl 2016-08-04 0:33 ` Chanwoo Choi 2016-08-04 0:33 ` Chanwoo Choi 2016-07-29 7:57 ` [PATCH v4 7/7] drm/rockchip: Add dmc notifier in vop driver Lin Huang 2016-07-29 7:57 ` Lin Huang 2016-08-01 7:39 ` [PATCH v4 0/7] rk3399 support ddr frequency scaling Chanwoo Choi 2016-08-01 7:39 ` Chanwoo Choi 2016-08-01 7:39 ` Chanwoo Choi 2016-08-01 7:46 ` hl 2016-08-01 7:46 ` hl 2016-08-01 7:46 ` hl 2016-08-01 7:50 ` Chanwoo Choi 2016-08-01 7:50 ` Chanwoo Choi 2016-08-01 7:50 ` Chanwoo Choi 2016-08-05 13:48 ` Tomeu Vizoso 2016-08-05 13:48 ` Tomeu Vizoso 2016-08-05 13:48 ` Tomeu Vizoso
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