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From: Xing Zheng <zhengxing@rock-chips.com>
To: heiko@sntech.de
Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org,
	briannorris@chromium.org, huangtao@rock-chips.com,
	zhangqing@rock-chips.com, Xing Zheng <zhengxing@rock-chips.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Date: Mon,  1 Aug 2016 11:37:21 +0800	[thread overview]
Message-ID: <1470022644-2152-4-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1470022644-2152-1-git-send-email-zhengxing@rock-chips.com>

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..ad3860a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
 	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-			RK3399_CLKGATE_CON(6), 12, GFLAGS),
-	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 13, GFLAGS),
+	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+			RK3399_CLKGATE_CON(6), 12, GFLAGS),
 	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org
Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Michael Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Date: Mon,  1 Aug 2016 11:37:21 +0800	[thread overview]
Message-ID: <1470022644-2152-4-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1470022644-2152-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..ad3860a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
 	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-			RK3399_CLKGATE_CON(6), 12, GFLAGS),
-	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 13, GFLAGS),
+	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+			RK3399_CLKGATE_CON(6), 12, GFLAGS),
 	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: zhengxing@rock-chips.com (Xing Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Date: Mon,  1 Aug 2016 11:37:21 +0800	[thread overview]
Message-ID: <1470022644-2152-4-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1470022644-2152-1-git-send-email-zhengxing@rock-chips.com>

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..ad3860a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
 	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-			RK3399_CLKGATE_CON(6), 12, GFLAGS),
-	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 13, GFLAGS),
+	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+			RK3399_CLKGATE_CON(6), 12, GFLAGS),
 	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

  parent reply	other threads:[~2016-08-01  3:49 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-01  3:37 [PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng
2016-08-01  3:37 ` Xing Zheng
2016-08-01  3:37 ` Xing Zheng
2016-08-01  3:37 ` [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng
2016-08-01  3:37   ` Xing Zheng
2016-08-01  3:37 ` [PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng
2016-08-01  3:37   ` Xing Zheng
2016-08-01  3:37   ` Xing Zheng
2016-08-01  3:37 ` Xing Zheng [this message]
2016-08-01  3:37   ` [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng
2016-08-01  3:37   ` Xing Zheng
2016-08-01  3:37 ` [PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng
2016-08-01  3:37   ` Xing Zheng
2016-08-01  3:37   ` Xing Zheng
2016-08-01  3:46 ` [PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng
2016-08-01  3:46   ` Xing Zheng
2016-08-01  3:46   ` Xing Zheng
2016-08-01  3:46 ` [PATCH 6/6] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng
2016-08-01  3:46   ` Xing Zheng
2016-08-01  3:46   ` Xing Zheng

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