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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [CI 11/26] drm/i915: Update the GGTT size/alignment query functions
Date: Thu,  4 Aug 2016 16:32:27 +0100	[thread overview]
Message-ID: <1470324762-2545-11-git-send-email-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <1470324762-2545-1-git-send-email-chris@chris-wilson.co.uk>

In order to be consistent with other address space functions, we want to
pass around 64-bit sizes, even though all known global GTT are limited
to 4GiB. Similarly, we are trying to be consistent in using the _ggtt_
nomenclature when referring to the special global GTT.

v2: Update docs to consistently state "global GTT".

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h        |  8 ++--
 drivers/gpu/drm/i915/i915_gem.c        | 81 +++++++++++++++++++---------------
 drivers/gpu/drm/i915/i915_gem_tiling.c |  3 +-
 3 files changed, 51 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e1369319326..b6e56ecb8637 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3241,11 +3241,9 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 
-uint32_t
-i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
-uint32_t
-i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
-			    int tiling_mode, bool fenced);
+u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode);
+u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,
+				int tiling_mode, bool fenced);
 
 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
 				    enum i915_cache_level cache_level);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index eedb80451dd5..0be3c5e4d307 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1847,46 +1847,57 @@ i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
 		i915_gem_release_mmap(obj);
 }
 
-uint32_t
-i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
+/**
+ * i915_gem_get_ggtt_size - return required global GTT size for an object
+ * @dev: drm device
+ * @size: object size
+ * @tiling_mode: tiling mode
+ *
+ * Return the required global GTT size for an object, taking into account
+ * potential fence register mapping.
+ */
+u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode)
 {
-	uint32_t gtt_size;
+	u64 ggtt_size;
 
-	if (INTEL_INFO(dev)->gen >= 4 ||
+	GEM_BUG_ON(size == 0);
+
+	if (INTEL_GEN(dev) >= 4 ||
 	    tiling_mode == I915_TILING_NONE)
 		return size;
 
 	/* Previous chips need a power-of-two fence region when tiling */
 	if (IS_GEN3(dev))
-		gtt_size = 1024*1024;
+		ggtt_size = 1024*1024;
 	else
-		gtt_size = 512*1024;
+		ggtt_size = 512*1024;
 
-	while (gtt_size < size)
-		gtt_size <<= 1;
+	while (ggtt_size < size)
+		ggtt_size <<= 1;
 
-	return gtt_size;
+	return ggtt_size;
 }
 
 /**
- * i915_gem_get_gtt_alignment - return required GTT alignment for an object
+ * i915_gem_get_ggtt_alignment - return required global GTT alignment
  * @dev: drm device
  * @size: object size
  * @tiling_mode: tiling mode
- * @fenced: is fenced alignemned required or not
+ * @fenced: is fenced alignment required or not
  *
- * Return the required GTT alignment for an object, taking into account
+ * Return the required global GTT alignment for an object, taking into account
  * potential fence register mapping.
  */
-uint32_t
-i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
-			   int tiling_mode, bool fenced)
+u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,
+				int tiling_mode, bool fenced)
 {
+	GEM_BUG_ON(size == 0);
+
 	/*
 	 * Minimum alignment is 4k (GTT page size), but might be greater
 	 * if a fence register is needed for the object.
 	 */
-	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
+	if (INTEL_GEN(dev) >= 4 || (!fenced && IS_G33(dev)) ||
 	    tiling_mode == I915_TILING_NONE)
 		return 4096;
 
@@ -1894,7 +1905,7 @@ i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
 	 * Previous chips need to be aligned to the size of the smallest
 	 * fence register that can contain the object.
 	 */
-	return i915_gem_get_gtt_size(dev, size, tiling_mode);
+	return i915_gem_get_ggtt_size(dev, size, tiling_mode);
 }
 
 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
@@ -2984,17 +2995,17 @@ i915_gem_object_insert_into_vm(struct drm_i915_gem_object *obj,
 
 		view_size = i915_ggtt_view_size(obj, ggtt_view);
 
-		fence_size = i915_gem_get_gtt_size(dev,
-						   view_size,
-						   obj->tiling_mode);
-		fence_alignment = i915_gem_get_gtt_alignment(dev,
-							     view_size,
-							     obj->tiling_mode,
-							     true);
-		unfenced_alignment = i915_gem_get_gtt_alignment(dev,
-								view_size,
-								obj->tiling_mode,
-								false);
+		fence_size = i915_gem_get_ggtt_size(dev,
+						    view_size,
+						    obj->tiling_mode);
+		fence_alignment = i915_gem_get_ggtt_alignment(dev,
+							      view_size,
+							      obj->tiling_mode,
+							      true);
+		unfenced_alignment = i915_gem_get_ggtt_alignment(dev,
+								 view_size,
+								 obj->tiling_mode,
+								 false);
 		size = max(size, view_size);
 		if (flags & PIN_MAPPABLE)
 			size = max_t(u64, size, fence_size);
@@ -3698,13 +3709,13 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
 	bool mappable, fenceable;
 	u32 fence_size, fence_alignment;
 
-	fence_size = i915_gem_get_gtt_size(obj->base.dev,
-					   obj->base.size,
-					   obj->tiling_mode);
-	fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
-						     obj->base.size,
-						     obj->tiling_mode,
-						     true);
+	fence_size = i915_gem_get_ggtt_size(obj->base.dev,
+					    obj->base.size,
+					    obj->tiling_mode);
+	fence_alignment = i915_gem_get_ggtt_alignment(obj->base.dev,
+						      obj->base.size,
+						      obj->tiling_mode,
+						      true);
 
 	fenceable = (vma->node.size == fence_size &&
 		     (vma->node.start & (fence_alignment - 1)) == 0);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index fa2eb4a4f212..4e42da691e4e 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -133,7 +133,8 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 			return false;
 	}
 
-	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
+	size = i915_gem_get_ggtt_size(obj->base.dev,
+				      obj->base.size, tiling_mode);
 	if (i915_gem_obj_ggtt_size(obj) != size)
 		return false;
 
-- 
2.8.1

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  parent reply	other threads:[~2016-08-04 15:33 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-04 15:32 [CI 01/26] drm/i915: Combine loops within i915_gem_evict_something Chris Wilson
2016-08-04 15:32 ` [CI 02/26] drm/i915: Remove surplus drm_device parameter to i915_gem_evict_something() Chris Wilson
2016-08-04 15:32 ` [CI 03/26] drm/i915: Double check the active status on the batch pool Chris Wilson
2016-08-04 15:32 ` [CI 04/26] drm/i915: Remove request retirement before each batch Chris Wilson
2016-08-04 15:32 ` [CI 05/26] drm/i915: Remove i915_gem_execbuffer_retire_commands() Chris Wilson
2016-08-04 15:32 ` [CI 06/26] drm/i915: Fix up vma alignment to be u64 Chris Wilson
2016-08-04 15:32 ` [CI 07/26] drm/i915: Pad GTT views of exec objects up to user specified size Chris Wilson
2016-08-04 15:32 ` [CI 08/26] drm/i915: Reduce WARN(i915_gem_valid_gtt_space) to a debug-only check Chris Wilson
2016-08-04 15:32 ` [CI 09/26] drm/i915: Split insertion/binding of an object into the VM Chris Wilson
2016-08-04 15:32 ` [CI 10/26] drm/i915: Convert 4096 alignment request to 0 for drm_mm allocations Chris Wilson
2016-08-04 15:32 ` Chris Wilson [this message]
2016-08-04 15:32 ` [CI 12/26] drm/i915: Update i915_gem_get_ggtt_size/_alignment to use drm_i915_private Chris Wilson
2016-08-04 15:32 ` [CI 13/26] drm/i915: Record allocated vma size Chris Wilson
2016-08-04 15:32 ` [CI 14/26] drm/i915: Wrap vma->pin_count accessors with small inline helpers Chris Wilson
2016-08-04 15:32 ` [CI 15/26] drm/i915: Start passing around i915_vma from execbuffer Chris Wilson
2016-08-04 15:32 ` [CI 16/26] drm/i915: Combine all i915_vma bitfields into a single set of flags Chris Wilson
2016-08-04 15:32 ` [CI 17/26] drm/i915: Make i915_vma_pin() small and inline Chris Wilson
2016-08-04 15:32 ` [CI 18/26] drm/i915: Remove highly confusing i915_gem_obj_ggtt_pin() Chris Wilson
2016-08-04 15:32 ` [CI 19/26] drm/i915: Separate intel_frontbuffer into its own header Chris Wilson
2016-08-04 15:32 ` [CI 20/26] drm/i915: Make fb_tracking.lock a spinlock Chris Wilson
2016-08-04 15:32 ` [CI 21/26] drm/i915: Use atomics to manipulate obj->frontbuffer_bits Chris Wilson
2016-08-04 15:32 ` [CI 22/26] drm/i915: Use dev_priv consistently through the intel_frontbuffer interface Chris Wilson
2016-08-04 15:32 ` [CI 23/26] drm/i915: Move obj->active:5 to obj->flags Chris Wilson
2016-08-04 15:32 ` [CI 24/26] drm/i915: Move i915_gem_object_wait_rendering() Chris Wilson
2016-08-04 15:32 ` [CI 25/26] drm/i915: Enable lockless lookup of request tracking via RCU Chris Wilson
2016-08-04 15:32 ` [CI 26/26] drm/i915: Export our request as a dma-buf fence on the reservation object Chris Wilson
2016-08-04 16:11 ` ✗ Ro.CI.BAT: failure for series starting with [CI,01/26] drm/i915: Combine loops within i915_gem_evict_something Patchwork
2016-08-04 16:15   ` Chris Wilson
  -- strict thread matches above, loose matches on Subject: below --
2016-08-04  7:32 [CI 01/26] " Chris Wilson
2016-08-04  7:33 ` [CI 11/26] drm/i915: Update the GGTT size/alignment query functions Chris Wilson

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