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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: agraf@suse.de, qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 03/45] target-ppc: add vector insert instructions
Date: Fri, 23 Sep 2016 17:14:39 +1000	[thread overview]
Message-ID: <1474614921-2221-4-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1474614921-2221-1-git-send-email-david@gibson.dropbear.id.au>

From: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>

The following vector insert instructions are added from ISA 3.0.

vinsertb - Vector Insert Byte
vinserth - Vector Insert Halfword
vinsertw - Vector Insert Word
vinsertd - Vector Insert Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/helper.h                 |  4 ++++
 target-ppc/int_helper.c             | 20 ++++++++++++++++++++
 target-ppc/translate.c              |  2 ++
 target-ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-ops.inc.c  | 18 +++++++++++++-----
 5 files changed, 71 insertions(+), 5 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index dcf3f95..5ae10bc 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -250,6 +250,10 @@ DEF_HELPER_2(vspltisw, void, avr, i32)
 DEF_HELPER_3(vspltb, void, avr, avr, i32)
 DEF_HELPER_3(vsplth, void, avr, avr, i32)
 DEF_HELPER_3(vspltw, void, avr, avr, i32)
+DEF_HELPER_3(vinsertb, void, avr, avr, i32)
+DEF_HELPER_3(vinserth, void, avr, avr, i32)
+DEF_HELPER_3(vinsertw, void, avr, avr, i32)
+DEF_HELPER_3(vinsertd, void, avr, avr, i32)
 DEF_HELPER_2(vupkhpx, void, avr, avr)
 DEF_HELPER_2(vupklpx, void, avr, avr)
 DEF_HELPER_2(vupkhsb, void, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 552b2e0..66a3d87 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1792,6 +1792,26 @@ VSPLT(w, u32)
 #undef VSPLT
 #undef SPLAT_ELEMENT
 #undef _SPLAT_MASKED
+#if defined(HOST_WORDS_BIGENDIAN)
+#define VINSERT(suffix, element)                                            \
+    void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
+    {                                                                       \
+        memmove(&r->u8[index], &b->u8[8 - sizeof(r->element)],              \
+               sizeof(r->element[0]));                                      \
+    }
+#else
+#define VINSERT(suffix, element)                                            \
+    void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
+    {                                                                       \
+        uint32_t d = (16 - index) - sizeof(r->element[0]);                  \
+        memmove(&r->u8[d], &b->u8[8], sizeof(r->element[0]));               \
+    }
+#endif
+VINSERT(b, u8)
+VINSERT(h, u16)
+VINSERT(w, u32)
+VINSERT(d, u64)
+#undef VINSERT
 
 #define VSPLTI(suffix, element, splat_type)                     \
     void helper_vspltis##suffix(ppc_avr_t *r, uint32_t splat)   \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f01ce1e..a27f455 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -498,6 +498,8 @@ EXTRACT_HELPER(UIMM, 0, 16);
 EXTRACT_HELPER(SIMM5, 16, 5);
 /* 5 bits signed immediate value */
 EXTRACT_HELPER(UIMM5, 16, 5);
+/* 4 bits unsigned immediate value */
+EXTRACT_HELPER(UIMM4, 16, 4);
 /* Bit count */
 EXTRACT_HELPER(NB, 11, 5);
 /* Shift count */
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index b984122..59ae68a 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -639,13 +639,45 @@ static void glue(gen_, name)(DisasContext *ctx)                         \
         tcg_temp_free_ptr(rd);                                          \
     }
 
+#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max)              \
+static void glue(gen_, name)(DisasContext *ctx)                         \
+    {                                                                   \
+        TCGv_ptr rb, rd;                                                \
+        uint8_t uimm = UIMM4(ctx->opcode);                              \
+        TCGv_i32 t0 = tcg_temp_new_i32();                               \
+        if (unlikely(!ctx->altivec_enabled)) {                          \
+            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
+            return;                                                     \
+        }                                                               \
+        if (uimm > splat_max) {                                         \
+            uimm = 0;                                                   \
+        }                                                               \
+        tcg_gen_movi_i32(t0, uimm);                                     \
+        rb = gen_avr_ptr(rB(ctx->opcode));                              \
+        rd = gen_avr_ptr(rD(ctx->opcode));                              \
+        gen_helper_##name(rd, rb, t0);                                  \
+        tcg_temp_free_i32(t0);                                          \
+        tcg_temp_free_ptr(rb);                                          \
+        tcg_temp_free_ptr(rd);                                          \
+    }
+
 GEN_VXFORM_UIMM(vspltb, 6, 8);
 GEN_VXFORM_UIMM(vsplth, 6, 9);
 GEN_VXFORM_UIMM(vspltw, 6, 10);
+GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
+GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
+GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
+GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
+GEN_VXFORM_DUAL(vspltisb, PPC_NONE, PPC2_ALTIVEC_207,
+                      vinsertb, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vspltish, PPC_NONE, PPC2_ALTIVEC_207,
+                      vinserth, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM_DUAL(vspltisw, PPC_NONE, PPC2_ALTIVEC_207,
+                      vinsertw, PPC_NONE, PPC2_ISA300);
 
 static void gen_vsldoi(DisasContext *ctx)
 {
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index 2a9f225..e6abeae 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -41,6 +41,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
 #define GEN_VXFORM_300(name, opc2, opc3)                                \
 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
 
+#define GEN_VXFORM_300_EXT(name, opc2, opc3, inval)                     \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
+
 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
 
@@ -191,11 +194,16 @@ GEN_VXRFORM(vcmpgefp, 3, 7)
 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
 
-#define GEN_VXFORM_SIMM(name, opc2, opc3)                               \
-    GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
-GEN_VXFORM_SIMM(vspltisb, 6, 12),
-GEN_VXFORM_SIMM(vspltish, 6, 13),
-GEN_VXFORM_SIMM(vspltisw, 6, 14),
+#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \
+GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \
+                                                               PPC_NONE)
+GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000,
+                                               PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
+                                               PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
+                                               PPC2_ALTIVEC_207),
+GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
 
 #define GEN_VXFORM_NOA(name, opc2, opc3)                                \
     GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
-- 
2.7.4

  parent reply	other threads:[~2016-09-23  7:16 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-23  7:14 [Qemu-devel] [PULL 00/45] ppc-for-2.8 queue 20160923 David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 01/45] MAINTAINERS: Add some missing ppc-related files David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 02/45] ppc: restrict the use of the rfi instruction David Gibson
2016-09-23  7:14 ` David Gibson [this message]
2016-09-23  7:14 ` [Qemu-devel] [PULL 04/45] target-ppc: add vector extract instructions David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 05/45] target-ppc: add vector count trailing zeros instructions David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 07/45] target-ppc: add vector permute right indexed instruction David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 08/45] ppc: Fix signal delivery in ppc-user and ppc64-user David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 09/45] qtest: replace strtoXX() by qemu_strtoXX() David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 10/45] libqos: define SPAPR libqos functions David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 11/45] tests: add RTAS command in the protocol David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 12/45] MAINTAINERS: add sPAPR tests David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 13/45] adb-keys.h: initial commit David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 14/45] adb.c: add support for QKeyCode David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 15/45] adb.c: correct several key assignments David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 16/45] adb.c: prevent NO_KEY value from going to guest David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 17/45] spapr_drc: convert to trace framework instead of DPRINTF David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 18/45] spapr_rtas: " David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 19/45] spapr_vio: " David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 20/45] spapr_llan: " David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 21/45] spapr_vscsi: " David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 22/45] target-ppc: consolidate load operations David Gibson
2016-09-23  7:14 ` [Qemu-devel] [PULL 23/45] target-ppc: convert ld64 to use new macro David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 24/45] target-ppc: convert ld[16, 32, 64]ur " David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 25/45] target-ppc: consolidate store operations David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 26/45] target-ppc: convert st64 to use new macro David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 27/45] target-ppc: convert st[16, 32, 64]r " David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 28/45] target-ppc: consolidate load with reservation David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 29/45] target-ppc: move out stqcx impementation David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 30/45] target-ppc: consolidate store conditional David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 31/45] target-ppc: add xxspltib instruction David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 32/45] target-ppc: add lxsi[bw]zx instruction David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 33/45] target-ppc: add stxsi[bh]x instruction David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 34/45] target-ppc: implement darn instruction David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 35/45] spapr: Introduce sPAPRCPUCoreClass David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 36/45] target-ppc: add TLB_NEED_LOCAL_FLUSH flag David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 37/45] target-ppc: add flag in check_tlb_flush() David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 38/45] target-ppc: tlbie/tlbivax should have global effect David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 39/45] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64 David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 40/45] ppc/xics: account correct irq status David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 41/45] ppc/xics: An ICS with offset 0 is assumed to be uninitialized David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 42/45] ppc/kvm: Mark 64kB page size support as disabled if not available David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 44/45] monitor: fix crash for platforms without a CPU 0 David Gibson
2016-09-23  7:15 ` [Qemu-devel] [PULL 45/45] spapr_pci: Add numa node id David Gibson
2016-09-23  8:28 ` [Qemu-devel] [PULL 00/45] ppc-for-2.8 queue 20160923 no-reply
2016-09-23 14:27 ` Peter Maydell

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