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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [Qemu-devel] [PATCH 05/16] target-sparc: Handle more twinx asis
Date: Mon, 10 Oct 2016 10:16:57 -0500	[thread overview]
Message-ID: <1476112628-12241-6-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1476112628-12241-1-git-send-email-rth@twiddle.net>

As used by HelenOS, presumably for ultra 2 and 3,
prior to the sun4v platform and the current twinx names.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-sparc/translate.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 86432ac..e7e07de 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2077,12 +2077,16 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
         case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
         case ASI_TWINX_REAL:   /* Real address, twinx */
         case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
+        case ASI_QUAD_LDD_PHYS:
+        case ASI_QUAD_LDD_PHYS_L:
             mem_idx = MMU_PHYS_IDX;
             break;
         case ASI_N:  /* Nucleus */
         case ASI_NL: /* Nucleus LE */
         case ASI_TWINX_N:
         case ASI_TWINX_NL:
+        case ASI_NUCLEUS_QUAD_LDD:
+        case ASI_NUCLEUS_QUAD_LDD_L:
             mem_idx = MMU_NUCLEUS_IDX;
             break;
         case ASI_AIUP:  /* As if user primary */
@@ -2164,6 +2168,10 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
         case ASI_TWINX_PL:
         case ASI_TWINX_S:
         case ASI_TWINX_SL:
+        case ASI_QUAD_LDD_PHYS:
+        case ASI_QUAD_LDD_PHYS_L:
+        case ASI_NUCLEUS_QUAD_LDD:
+        case ASI_NUCLEUS_QUAD_LDD_L:
             type = GET_ASI_DTWINX;
             break;
         case ASI_BLK_COMMIT_P:
-- 
2.7.4

  parent reply	other threads:[~2016-10-10 15:17 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-10 15:16 [Qemu-devel] [PATCH 00/16] target-sparc improvements Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 01/16] target-sparc: Use overalignment flags for twinx and block asis Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 02/16] target-sparc: Introduce cpu_raise_exception_ra Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 03/16] target-sparc: Add MMU_PHYS_IDX Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 04/16] target-sparc: Use MMU_PHYS_IDX for bypass asis Richard Henderson
2016-10-10 15:16 ` Richard Henderson [this message]
2016-10-10 15:16 ` [Qemu-devel] [PATCH 06/16] target-sparc: Implement swap_asi inline Richard Henderson
2016-10-10 15:16 ` [Qemu-devel] [PATCH 07/16] target-sparc: Implement ldstub_asi inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 08/16] target-sparc: Implement cas_asi/casx_asi inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 09/16] target-sparc: Implement BCOPY/BFILL inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 10/16] target-sparc: Remove asi helper code handled inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 11/16] target-sparc: Implement ldqf and stqf inline Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 12/16] target-sparc: Allow 4-byte alignment on fp mem ops Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 13/16] target-sparc: Remove MMU_MODE*_SUFFIX Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 14/16] target-sparc: Optmize writeback of cpu_cond Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 15/16] target-sparc: Use tcg_gen_atomic_xchg_tl Richard Henderson
2016-10-10 15:17 ` [Qemu-devel] [PATCH 16/16] target-sparc: Use tcg_gen_atomic_cmpxchg_tl Richard Henderson
2016-10-10 17:02 ` [Qemu-devel] [PATCH 00/16] target-sparc improvements no-reply
2016-10-11 21:42 ` Mark Cave-Ayland
2016-10-12  1:42   ` Richard Henderson
2016-10-15  8:08     ` Mark Cave-Ayland

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