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From: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Wenrui Li <wenrui.li-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Brian Norris
	<briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH v7 1/3] Documentation/devicetree: Add new property to specify the max link speed
Date: Wed, 12 Oct 2016 10:01:23 +0800	[thread overview]
Message-ID: <1476237685-14539-1-git-send-email-shawn.lin@rock-chips.com> (raw)

Some of the host drivers have the requirement of knowing whether the
EP would never train at some link speed at all. For instance, on some
boards, the link won't train at 5 GT/s but the host driver still sacrifice
some cycle to wait for the resule of training at 5 GT/s as the host could
actually support 5 GT/s. So we could parse this new property and make the
host drivers be aware of these cases.

Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 08dcfad..e7d97a3 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -18,3 +18,9 @@ driver implementation may support the following properties:
    host bridges in the system, otherwise potentially conflicting domain numbers
    may be assigned to root buses behind different host bridges.  The domain
    number for each host bridge in the system must be unique.
+- max-link-speed:
+   If present this property specifies PCI gen for link capability. The host drivers
+   could add this as a strategy to avoid unnecessary operation for unsupported
+   link speed, for instance, trying to do training for unsupported link speed, etc.
+   Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other
+   values are invalid.
-- 
2.3.7

WARNING: multiple messages have this Message-ID (diff)
From: Shawn Lin <shawn.lin@rock-chips.com>
To: Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
	Rajat Jain <rajatja@google.com>,
	Wenrui Li <wenrui.li@rock-chips.com>,
	Brian Norris <briannorris@chromium.org>,
	devicetree@vger.kernel.org, Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH v7 1/3] Documentation/devicetree: Add new property to specify the max link speed
Date: Wed, 12 Oct 2016 10:01:23 +0800	[thread overview]
Message-ID: <1476237685-14539-1-git-send-email-shawn.lin@rock-chips.com> (raw)

Some of the host drivers have the requirement of knowing whether the
EP would never train at some link speed at all. For instance, on some
boards, the link won't train at 5 GT/s but the host driver still sacrifice
some cycle to wait for the resule of training at 5 GT/s as the host could
actually support 5 GT/s. So we could parse this new property and make the
host drivers be aware of these cases.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 08dcfad..e7d97a3 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -18,3 +18,9 @@ driver implementation may support the following properties:
    host bridges in the system, otherwise potentially conflicting domain numbers
    may be assigned to root buses behind different host bridges.  The domain
    number for each host bridge in the system must be unique.
+- max-link-speed:
+   If present this property specifies PCI gen for link capability. The host drivers
+   could add this as a strategy to avoid unnecessary operation for unsupported
+   link speed, for instance, trying to do training for unsupported link speed, etc.
+   Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other
+   values are invalid.
-- 
2.3.7



             reply	other threads:[~2016-10-12  2:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-12  2:01 Shawn Lin [this message]
2016-10-12  2:01 ` [PATCH v7 1/3] Documentation/devicetree: Add new property to specify the max link speed Shawn Lin
     [not found] ` <1476237685-14539-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-10-12  2:01   ` [PATCH v7 2/3] of/pci: Add helper function to parse max-link-speed from dt Shawn Lin
2016-10-12  2:01     ` Shawn Lin
2016-10-12  2:01   ` [PATCH v7 3/3] PCI: rockchip: Specify the link capability Shawn Lin
2016-10-12  2:01     ` Shawn Lin

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