From: Chanwoo Choi <cw00.choi@samsung.com> To: krzk@kernel.org, javier@osg.samsung.com, kgene@kernel.org, robh+dt@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: cw00.choi@samsung.com, myungjoo.ham@samsung.com, kyungmin.park@samsung.com, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: exynos5433: Add bus dt node using VDD_INT for Exynos5433 Date: Thu, 08 Dec 2016 13:58:10 +0900 [thread overview] Message-ID: <1481173091-9728-5-git-send-email-cw00.choi@samsung.com> (raw) In-Reply-To: <1481173091-9728-1-git-send-email-cw00.choi@samsung.com> This patch adds the bus nodes using VDD_INT for Exynos5433 SoC. Exynos5433 has the following AMBA AXI buses to translate data between DRAM and sub-blocks. Following list specify the detailed correlation between sub-block and clock: - CLK_ACLK_G2D_{400|266} : Bus clock for G2D (2D graphic engine) - CLK_ACLK_MSCL_400 : Bus clock for MSCL (Memory to memory Scaler) - CLK_ACLK_GSCL_333 : Bus clock for GSCL (General Scaler) - CLK_SCLK_JPEG_MSCL : Bus clock for JPEG - CLK_ACLK_MFC_400 : Bus clock for MFC (Multi Format Codec) - CLK_ACLK_HEVC_400 : Bus clock for HEVC (High Efficient Video Codec) - CLK_ACLK_BUS0_400 : NoC(Network On Chip)'s bus clock for PERIC/PERIS/FSYS/MSCL - CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D - CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi | 197 +++++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 + 2 files changed, 198 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi new file mode 100644 index 000000000000..09dac0124f73 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi @@ -0,0 +1,197 @@ +/* + * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * Chanwoo Choi <cw00.choi@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&soc { + bus_g2d_400: bus0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_G2D_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_g2d_266: bus1 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_G2D_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_266_opp_table>; + status ="disabled"; + }; + + bus_gscl: bus2 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_GSCL_333>; + clock-names = "bus"; + operating-points-v2 = <&bus_gscl_opp_table>; + status ="disabled"; + }; + + bus_hevc: bus3 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_HEVC_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_hevc_opp_table>; + status ="disabled"; + }; + + bus_jpeg: bus4 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_mfc: bus5 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_MFC_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_mscl: bus6 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_MSCL_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_noc0: bus7 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_hevc_opp_table>; + status ="disabled"; + }; + + bus_noc1: bus8 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_hevc_opp_table>; + status ="disabled"; + }; + + bus_noc2: bus9 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_mif CLK_ACLK_BUS2_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_noc2_opp_table>; + status ="disabled"; + }; + + bus_g2d_400_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1075000>; + }; + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <975000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <962500>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <950000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <937500>; + }; + }; + + bus_g2d_266_opp_table: opp_table3 { + compatible = "operating-points-v2"; + + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_gscl_opp_table: opp_table4 { + compatible = "operating-points-v2"; + + opp@333000000 { + opp-hz = /bits/ 64 <333000000>; + }; + opp@222000000 { + opp-hz = /bits/ 64 <222000000>; + }; + opp@166500000 { + opp-hz = /bits/ 64 <166500000>; + }; + }; + + bus_hevc_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp@267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_noc2_opp_table: opp_table6 { + compatible = "operating-points-v2"; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8c4ee84d5232..68f764e5851c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1482,5 +1482,6 @@ }; }; +#include "exynos5433-bus.dtsi" #include "exynos5433-pinctrl.dtsi" #include "exynos5433-tmu.dtsi" -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: cw00.choi@samsung.com (Chanwoo Choi) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/5] arm64: dts: exynos5433: Add bus dt node using VDD_INT for Exynos5433 Date: Thu, 08 Dec 2016 13:58:10 +0900 [thread overview] Message-ID: <1481173091-9728-5-git-send-email-cw00.choi@samsung.com> (raw) In-Reply-To: <1481173091-9728-1-git-send-email-cw00.choi@samsung.com> This patch adds the bus nodes using VDD_INT for Exynos5433 SoC. Exynos5433 has the following AMBA AXI buses to translate data between DRAM and sub-blocks. Following list specify the detailed correlation between sub-block and clock: - CLK_ACLK_G2D_{400|266} : Bus clock for G2D (2D graphic engine) - CLK_ACLK_MSCL_400 : Bus clock for MSCL (Memory to memory Scaler) - CLK_ACLK_GSCL_333 : Bus clock for GSCL (General Scaler) - CLK_SCLK_JPEG_MSCL : Bus clock for JPEG - CLK_ACLK_MFC_400 : Bus clock for MFC (Multi Format Codec) - CLK_ACLK_HEVC_400 : Bus clock for HEVC (High Efficient Video Codec) - CLK_ACLK_BUS0_400 : NoC(Network On Chip)'s bus clock for PERIC/PERIS/FSYS/MSCL - CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D - CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi | 197 +++++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 + 2 files changed, 198 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi new file mode 100644 index 000000000000..09dac0124f73 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi @@ -0,0 +1,197 @@ +/* + * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * Chanwoo Choi <cw00.choi@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&soc { + bus_g2d_400: bus0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_G2D_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_g2d_266: bus1 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_G2D_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_266_opp_table>; + status ="disabled"; + }; + + bus_gscl: bus2 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_GSCL_333>; + clock-names = "bus"; + operating-points-v2 = <&bus_gscl_opp_table>; + status ="disabled"; + }; + + bus_hevc: bus3 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_HEVC_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_hevc_opp_table>; + status ="disabled"; + }; + + bus_jpeg: bus4 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_mfc: bus5 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_MFC_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_mscl: bus6 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_MSCL_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_g2d_400_opp_table>; + status ="disabled"; + }; + + bus_noc0: bus7 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_hevc_opp_table>; + status ="disabled"; + }; + + bus_noc1: bus8 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_hevc_opp_table>; + status ="disabled"; + }; + + bus_noc2: bus9 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_mif CLK_ACLK_BUS2_400>; + clock-names = "bus"; + operating-points-v2 = <&bus_noc2_opp_table>; + status ="disabled"; + }; + + bus_g2d_400_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1075000>; + }; + opp at 267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1000000>; + }; + opp at 200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <975000>; + }; + opp at 160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <962500>; + }; + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <950000>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <937500>; + }; + }; + + bus_g2d_266_opp_table: opp_table3 { + compatible = "operating-points-v2"; + + opp at 267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + opp at 200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp at 160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_gscl_opp_table: opp_table4 { + compatible = "operating-points-v2"; + + opp at 333000000 { + opp-hz = /bits/ 64 <333000000>; + }; + opp at 222000000 { + opp-hz = /bits/ 64 <222000000>; + }; + opp at 166500000 { + opp-hz = /bits/ 64 <166500000>; + }; + }; + + bus_hevc_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp at 400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp at 267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + opp at 200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp at 160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + + bus_noc2_opp_table: opp_table6 { + compatible = "operating-points-v2"; + + opp at 400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp at 200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp at 134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8c4ee84d5232..68f764e5851c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1482,5 +1482,6 @@ }; }; +#include "exynos5433-bus.dtsi" #include "exynos5433-pinctrl.dtsi" #include "exynos5433-tmu.dtsi" -- 1.9.1
next prev parent reply other threads:[~2016-12-08 4:58 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-12-08 4:58 [PATCH v2 0/5] arm64: dts: Enable bus frequency scaling on Exynos5433-based TM2 board Chanwoo Choi 2016-12-08 4:58 ` Chanwoo Choi 2016-12-08 4:58 ` [PATCH v2 1/5] clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical Chanwoo Choi 2016-12-08 4:58 ` Chanwoo Choi 2016-12-15 4:33 ` Chanwoo Choi 2016-12-15 4:33 ` Chanwoo Choi 2016-12-20 10:47 ` Sylwester Nawrocki 2016-12-20 10:47 ` Sylwester Nawrocki 2016-12-20 10:47 ` Sylwester Nawrocki 2016-12-29 15:16 ` Sylwester Nawrocki 2016-12-08 4:58 ` [PATCH v2 2/5] PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433 Chanwoo Choi 2016-12-08 4:58 ` Chanwoo Choi 2016-12-08 4:58 ` Chanwoo Choi 2016-12-08 4:58 ` [PATCH v2 3/5] arm64: dts: exynos5433: Add PPMU dt node Chanwoo Choi 2016-12-08 4:58 ` Chanwoo Choi 2017-01-02 18:33 ` Krzysztof Kozlowski 2017-01-02 18:33 ` Krzysztof Kozlowski 2017-01-02 18:33 ` Krzysztof Kozlowski 2016-12-08 4:58 ` Chanwoo Choi [this message] 2016-12-08 4:58 ` [PATCH v2 4/5] arm64: dts: exynos5433: Add bus dt node using VDD_INT for Exynos5433 Chanwoo Choi 2016-12-08 17:52 ` Krzysztof Kozlowski 2016-12-08 17:52 ` Krzysztof Kozlowski 2016-12-30 0:59 ` Chanwoo Choi 2016-12-30 0:59 ` Chanwoo Choi 2016-12-30 0:59 ` Chanwoo Choi 2016-12-30 14:51 ` Krzysztof Kozlowski 2016-12-30 14:51 ` Krzysztof Kozlowski 2016-12-30 15:08 ` Chanwoo Choi 2016-12-30 15:08 ` Chanwoo Choi 2017-01-02 18:35 ` Krzysztof Kozlowski 2017-01-02 18:35 ` Krzysztof Kozlowski 2016-12-08 4:58 ` [PATCH v2 5/5] arm64: dts: exynos5433: Add support of bus frequency using VDD_INT on TM2 Chanwoo Choi 2016-12-08 4:58 ` Chanwoo Choi 2017-01-02 18:37 ` Krzysztof Kozlowski 2017-01-02 18:37 ` Krzysztof Kozlowski 2017-01-02 18:37 ` Krzysztof Kozlowski
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