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From: John Hsu <KCHSU0@nuvoton.com>
To: broonie@kernel.org
Cc: alsa-devel@alsa-project.org, anatol.pomozov@gmail.com,
	YHCHuang@nuvoton.com, WTLI@nuvoton.com,
	John Hsu <KCHSU0@nuvoton.com>,
	lgirdwood@gmail.com, benzh@chromium.org, CTLIN0@nuvoton.com,
	mhkuo@nuvoton.com, yong.zhi@intel.com
Subject: [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode
Date: Tue, 20 Dec 2016 16:47:07 +0800	[thread overview]
Message-ID: <1482223627-23547-2-git-send-email-KCHSU0@nuvoton.com> (raw)
In-Reply-To: <1482223627-23547-1-git-send-email-KCHSU0@nuvoton.com>

Provide the LRC and BCLK divide. The clock divide needs configuration
properly when codec in master mode.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
---
 sound/soc/codecs/nau8825.c | 26 ++++++++++++++++++++++++++
 sound/soc/codecs/nau8825.h |  6 ++++++
 2 files changed, 32 insertions(+)

diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c
index 9c98d35..3c7a801 100644
--- a/sound/soc/codecs/nau8825.c
+++ b/sound/soc/codecs/nau8825.c
@@ -1421,9 +1421,35 @@ static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 	return 0;
 }
 
+static int nau8825_set_clkdiv(struct snd_soc_dai *codec_dai,
+	int div_id, int div)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
+
+	switch (div_id) {
+	case NAU8825_BCLKDIV:
+		regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
+			NAU8825_I2S_BLK_DIV_MASK, div);
+		break;
+
+	case NAU8825_FSDIV:
+		regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
+			NAU8825_I2S_LRC_DIV_MASK,
+			div << NAU8825_I2S_LRC_DIV_SFT);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static const struct snd_soc_dai_ops nau8825_dai_ops = {
 	.hw_params	= nau8825_hw_params,
 	.set_fmt	= nau8825_set_dai_fmt,
+	.set_clkdiv	= nau8825_set_clkdiv,
 };
 
 #define NAU8825_RATES	SNDRV_PCM_RATE_8000_192000
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h
index 4b390c4..58b8554 100644
--- a/sound/soc/codecs/nau8825.h
+++ b/sound/soc/codecs/nau8825.h
@@ -425,6 +425,12 @@
 #define NAU8825_CHANRGE_PUMP_EN	(1 << 5)
 
 
+/* Programmable divide */
+enum {
+	NAU8825_BCLKDIV,
+	NAU8825_FSDIV,
+};
+
 /* System Clock Source */
 enum {
 	NAU8825_CLK_DIS = 0,
-- 
2.6.4

  reply	other threads:[~2016-12-20  8:48 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-20  8:47 [PATCH 1/2] ASoC: nau8825: correct the function name of register John Hsu
2016-12-20  8:47 ` John Hsu [this message]
2016-12-31 18:57   ` [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode Mark Brown
2017-01-03  3:04     ` John Hsu
2017-01-09 11:42       ` Mark Brown
2017-01-23  8:39         ` John Hsu
2016-12-31 19:18 ` Applied "ASoC: nau8825: correct the function name of register" to the asoc tree Mark Brown

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