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From: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
To: catalin.marinas-5wv7dgnIgG8@public.gmane.org,
	will.deacon-5wv7dgnIgG8@public.gmane.org,
	marc.zyngier-5wv7dgnIgG8@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	stuart.yoder-3arQi8VN3Tc@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org
Cc: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Subject: [PATCH v5 1/6] arm64: arch_timer: Add device tree binding for hisilicon-161601 erratum
Date: Fri, 23 Dec 2016 15:04:24 +0800	[thread overview]
Message-ID: <1482476669-15596-2-git-send-email-dingtianhong@huawei.com> (raw)
In-Reply-To: <1482476669-15596-1-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

v2: Use the new erratum name and update the description.

Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..935f142 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@ to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161601 : A boolean property. Indicates the presence of
+  erratum 161601, which says that reading the counter is unreliable unless
+  reading twice on the register and the value of the second read is larger
+  than the first by less than 32. If the verification is unsuccessful, then
+  discard the value of this read and repeat this procedure until the verification
+  is successful.  This also affects writes to the tval register, due to the
+  implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
-- 
1.9.0


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WARNING: multiple messages have this Message-ID (diff)
From: dingtianhong@huawei.com (Ding Tianhong)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 1/6] arm64: arch_timer: Add device tree binding for hisilicon-161601 erratum
Date: Fri, 23 Dec 2016 15:04:24 +0800	[thread overview]
Message-ID: <1482476669-15596-2-git-send-email-dingtianhong@huawei.com> (raw)
In-Reply-To: <1482476669-15596-1-git-send-email-dingtianhong@huawei.com>

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

v2: Use the new erratum name and update the description.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..935f142 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,14 @@ to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161601 : A boolean property. Indicates the presence of
+  erratum 161601, which says that reading the counter is unreliable unless
+  reading twice on the register and the value of the second read is larger
+  than the first by less than 32. If the verification is unsuccessful, then
+  discard the value of this read and repeat this procedure until the verification
+  is successful.  This also affects writes to the tval register, due to the
+  implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
-- 
1.9.0

  parent reply	other threads:[~2016-12-23  7:04 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-23  7:04 [PATCH v5 0/6] arm64: arch_timer: Add workaround for hisilicon-161601 erratum Ding Tianhong
2016-12-23  7:04 ` Ding Tianhong
     [not found] ` <1482476669-15596-1-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-12-23  7:04   ` Ding Tianhong [this message]
2016-12-23  7:04     ` [PATCH v5 1/6] arm64: arch_timer: Add device tree binding " Ding Tianhong
2016-12-23  7:04   ` [PATCH v5 3/6] arm64: arch_timer: Work around Erratum Hisilicon-161601 Ding Tianhong
2016-12-23  7:04     ` Ding Tianhong
     [not found]     ` <1482476669-15596-4-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-12-24  6:07       ` Kefeng Wang
2016-12-24  6:07         ` Kefeng Wang
2016-12-23  7:04   ` [PATCH v5 6/6] arm64: arch_timer: acpi: add hisi timer errata data Ding Tianhong
2016-12-23  7:04     ` Ding Tianhong
     [not found]     ` <1482476669-15596-7-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-12-24  7:11       ` Kefeng Wang
2016-12-24  7:11         ` Kefeng Wang
2016-12-23  7:04 ` [PATCH v5 2/6] arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585 Ding Tianhong
2016-12-23  7:04   ` Ding Tianhong
2016-12-23  7:04 ` [PATCH v5 4/6] arm64: arch timer: Add timer erratum property for Hip05-d02 and Hip06-d03 Ding Tianhong
2016-12-23  7:04   ` Ding Tianhong
2016-12-23  7:04 ` [PATCH v5 5/6] arm64: arch_timer: apci: Introduce a generic aquirk framework for erratum Ding Tianhong
2016-12-23  7:04   ` Ding Tianhong
2017-01-03 10:03 ` [PATCH v5 0/6] arm64: arch_timer: Add workaround for hisilicon-161601 erratum Hanjun Guo
2017-01-03 10:03   ` Hanjun Guo
2017-01-03 13:24   ` Ding Tianhong
2017-01-03 13:24     ` Ding Tianhong

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