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From: vathsala nagaraju <vathsala.nagaraju@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2
Date: Fri, 30 Dec 2016 10:55:24 +0530	[thread overview]
Message-ID: <1483075524-25189-11-git-send-email-vathsala.nagaraju@intel.com> (raw)
In-Reply-To: <1483075524-25189-1-git-send-email-vathsala.nagaraju@intel.com>

PSR1 and PSR2 enable sequence are mutually exclusive.
Register SRD_PERF_COUNT increments while system is in psr1.
This register is not valid for psr2.while in psr2,SRD_PERF_COUNT
is always 0.
Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case.
Also, if dc6 is disabled via kernel parameter i915.enable_dc=0,
EDP_PSR_PERF_CNT can be reported for SKL+ platforms for debug
purpose.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 55bcdd2..265474d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2539,6 +2539,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	u32 stat[3];
 	enum pipe pipe;
 	bool enabled = false;
+	bool dc6_enabled = false;
 
 	if (!HAS_PSR(dev_priv)) {
 		seq_puts(m, "PSR not supported\n");
@@ -2598,11 +2599,20 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 	/*
 	 * VLV/CHV PSR has no kind of performance counter
+	 * EDP_PSR_PERF_CNT is not valid for psr2.
 	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
+	 * if we want to read EDP_PSR_PERF_CNT for debug purpose on SKL+,
+	 * disable dc state in kernel parameter i915.enable_dc=0.
 	 */
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+
+	dc6_enabled = ((I915_READ(DC_STATE_EN) &
+			DC_STATE_EN_UPTO_DC5_DC6_MASK) ==
+			DC_STATE_EN_UPTO_DC6);
+
+	if ((!dev_priv->psr.psr2_support && !dc6_enabled) ||
+	     IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
-			EDP_PSR_PERF_CNT_MASK;
+			  EDP_PSR_PERF_CNT_MASK;
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
 	}
-- 
1.9.1

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  parent reply	other threads:[~2016-12-30  5:26 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-30  5:25 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
2016-12-30  5:25 ` [PATCH 01/10] drm : adds Y-coordinate and Colorimetry Format vathsala nagaraju
2016-12-30 19:05   ` Daniel Vetter
2016-12-30  5:25 ` [PATCH 02/10] drm/i915/psr: program vsc header for psr2 vathsala nagaraju
2016-12-30  5:25 ` [PATCH 03/10] drm/i915/psr: fix blank screen issue " vathsala nagaraju
2016-12-30  5:25 ` [PATCH 04/10] drm/i915/psr: disable aux_frame_sync on psr2 exit vathsala nagaraju
2016-12-30  5:25 ` [PATCH 05/10] drm/i915/psr: enable ALPM for psr2 vathsala nagaraju
2016-12-30  5:25 ` [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS " vathsala nagaraju
2016-12-30  5:25 ` [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep vathsala nagaraju
2016-12-30  5:25 ` [PATCH 08/10] drm/i915/psr: enable psr2 for y cordinate panels vathsala nagaraju
2016-12-30  5:25 ` [PATCH 09/10] drm/i915/psr: report live PSR2 State vathsala nagaraju
2016-12-30  5:25 ` vathsala nagaraju [this message]
2016-12-30  5:53 ` ✓ Fi.CI.BAT: success for enable psr2 for idle_screen on y-cordinate panel Patchwork
2017-01-02 11:30 [PATCH 00/10] " vathsala nagaraju
2017-01-02 11:31 ` [PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2 vathsala nagaraju
2017-01-05 17:40   ` Rodrigo Vivi

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