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From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Archit Taneja <architt@codeaurora.org>
Subject: [PATCH 03/10] drm/msm/dsi: Add a PHY op that initializes version specific stuff
Date: Sat,  7 Jan 2017 18:40:35 +0530	[thread overview]
Message-ID: <1483794642-2184-4-git-send-email-architt@codeaurora.org> (raw)
In-Reply-To: <1483794642-2184-1-git-send-email-architt@codeaurora.org>

Create an init() op for dsi_phy which sets up things specific to
a given DSI PHY.

The dsi_phy driver probe expects every DSI version to get a
"dsi_phy_regulator" mmio base. This isn't the case for 8x96.
Creating an init() op will allow us to accommodate such
differences.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c           | 33 ++++++++++++++++++-------
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h           |  2 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c      |  1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c      |  2 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |  1 +
 5 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f39386e..03a3549 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
 	return -EINVAL;
 }
 
+int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
+{
+	struct platform_device *pdev = phy->pdev;
+	int ret = 0;
+
+	phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
+				"DSI_PHY_REG");
+	if (IS_ERR(phy->reg_base)) {
+		dev_err(&pdev->dev, "%s: failed to map phy regulator base\n",
+			__func__);
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+fail:
+	return ret;
+}
+
 static int dsi_phy_driver_probe(struct platform_device *pdev)
 {
 	struct msm_dsi_phy *phy;
@@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
 		goto fail;
 	}
 
-	phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
-				"DSI_PHY_REG");
-	if (IS_ERR(phy->reg_base)) {
-		dev_err(dev, "%s: failed to map phy regulator base\n",
-			__func__);
-		ret = -ENOMEM;
-		goto fail;
-	}
-
 	ret = dsi_phy_regulator_init(phy);
 	if (ret) {
 		dev_err(dev, "%s: failed to init regulator\n", __func__);
@@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
 		goto fail;
 	}
 
+	if (phy->cfg->ops.init) {
+		ret = phy->cfg->ops.init(phy);
+		if (ret)
+			goto fail;
+	}
+
 	/* PLL init will call into clk_register which requires
 	 * register access, so we need to enable power and ahb clock.
 	 */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f24a854..b9d7d02 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -22,6 +22,7 @@
 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
 
 struct msm_dsi_phy_ops {
+	int (*init) (struct msm_dsi_phy *phy);
 	int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
 		const unsigned long bit_rate, const unsigned long esc_rate);
 	void (*disable)(struct msm_dsi_phy *phy);
@@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
 	const unsigned long bit_rate, const unsigned long esc_rate);
 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
 				u32 bit_mask);
+int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
 
 #endif /* __DSI_PHY_H__ */
 
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index c757e20..c4a7be5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -145,6 +145,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
 	.ops = {
 		.enable = dsi_20nm_phy_enable,
 		.disable = dsi_20nm_phy_disable,
+		.init = msm_dsi_phy_init_common,
 	},
 	.io_start = { 0xfd998300, 0xfd9a0300 },
 	.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 63d7fba..ea740c5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -144,6 +144,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
 	.ops = {
 		.enable = dsi_28nm_phy_enable,
 		.disable = dsi_28nm_phy_disable,
+		.init = msm_dsi_phy_init_common,
 	},
 	.io_start = { 0xfd922b00, 0xfd923100 },
 	.num_dsi_phy = 2,
@@ -161,6 +162,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
 	.ops = {
 		.enable = dsi_28nm_phy_enable,
 		.disable = dsi_28nm_phy_disable,
+		.init = msm_dsi_phy_init_common,
 	},
 	.io_start = { 0x1a98500 },
 	.num_dsi_phy = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 7bdb9de..9aff0ba 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -191,6 +191,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
 	.ops = {
 		.enable = dsi_28nm_phy_enable,
 		.disable = dsi_28nm_phy_disable,
+		.init = msm_dsi_phy_init_common,
 	},
 	.io_start = { 0x4700300, 0x5800300 },
 	.num_dsi_phy = 2,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

  parent reply	other threads:[~2017-01-07 13:11 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-07 13:10 [PATCH 00/10] drm/msm/dsi: Dual DSI and 8x96 PHY/PLL support Archit Taneja
2017-01-07 13:10 ` [PATCH 01/10] drm/msm/dsi: Don't error if a DSI host doesn't have a device connected Archit Taneja
2017-01-07 13:10 ` [PATCH 02/10] drm/msm/dsi: Add 8x96 info in dsi_cfg Archit Taneja
2017-01-07 13:10 ` Archit Taneja [this message]
2017-01-07 13:10 ` [PATCH 04/10] drm/msm/dsi: Return more timings from PHY to host Archit Taneja
2017-01-07 13:10 ` [PATCH 05/10] drm/msm/dsi: Pass down use case to PHY Archit Taneja
2017-01-07 13:10 ` [PATCH 06/10] drm/msm/dsi: Reset both PHYs before clock operation for dual DSI Archit Taneja
2017-01-07 13:10 ` [PATCH 07/10] drm/msm/dsi: Move PHY operations out of host Archit Taneja
2017-01-07 13:10 ` [PATCH 08/10] drm/msm/dsi: Udpate generated headers for 14nm PHY and PLL Archit Taneja
2017-01-07 13:10 ` [PATCH 09/10] drm/msm/dsi: Add new method to calculate 14nm PHY timings Archit Taneja
2017-01-07 13:10 ` [PATCH 10/10] drm/msm/dsi: Add PHY/PLL for 8x96 Archit Taneja
2017-01-19 20:17   ` Stephen Boyd
2017-01-23  4:06     ` Archit Taneja
2017-01-25  4:09   ` [PATCH v2 " Archit Taneja

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