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From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PULL v2 9/9] target-m68k: increment/decrement with SP
Date: Sat, 14 Jan 2017 10:07:58 +0100	[thread overview]
Message-ID: <1484384878-29179-10-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1484384878-29179-1-git-send-email-laurent@vivier.eu>

On 680x0 family only.

Address Register indirect With postincrement:

When using the stack pointer (A7) with byte size data, the register
is incremented by two.

Address Register indirect With predecrement:

When using the stack pointer (A7) with byte size data, the register
is decremented by two.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
---
 target/m68k/translate.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index cf5d8dd..9f60fbc 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -725,7 +725,12 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
         }
         reg = get_areg(s, reg0);
         tmp = tcg_temp_new();
-        tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
+        if (reg0 == 7 && opsize == OS_BYTE &&
+            m68k_feature(s->env, M68K_FEATURE_M68000)) {
+            tcg_gen_subi_i32(tmp, reg, 2);
+        } else {
+            tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
+        }
         return tmp;
     case 5: /* Indirect displacement.  */
         reg = get_areg(s, reg0);
@@ -801,7 +806,12 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
         result = gen_ldst(s, opsize, reg, val, what);
         if (what == EA_STORE || !addrp) {
             TCGv tmp = tcg_temp_new();
-            tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
+            if (reg0 == 7 && opsize == OS_BYTE &&
+                m68k_feature(s->env, M68K_FEATURE_M68000)) {
+                tcg_gen_addi_i32(tmp, reg, 2);
+            } else {
+                tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
+            }
             delay_set_areg(s, reg0, tmp, true);
         }
         return result;
-- 
2.7.4

  parent reply	other threads:[~2017-01-14  9:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-14  9:07 [Qemu-devel] [PULL v2 0/9] M68k for 2.9 patches Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 1/9] target-m68k: Implement bitfield ops for registers Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 2/9] target-m68k: Implement bitfield ops for memory Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 3/9] target-m68k: Implement bfffo Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 4/9] m68k: Remove PCI and USB from config file Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 5/9] target-m68k: fix bit operation with immediate value Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 6/9] target-m68k: fix gen_flush_flags() Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 7/9] target-m68k: manage pre-dec et post-inc in CAS Laurent Vivier
2017-01-14  9:07 ` [Qemu-devel] [PULL v2 8/9] target-m68k: CAS doesn't need aligned access Laurent Vivier
2017-01-14  9:07 ` Laurent Vivier [this message]
2017-01-17 11:19 ` [Qemu-devel] [PULL v2 0/9] M68k for 2.9 patches Peter Maydell

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