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From: Will Deacon <will.deacon@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: marc.zyngier@arm.com, mark.rutland@arm.com, kim.phillips@arm.com,
	alex.bennee@linaro.org, christoffer.dall@linaro.org,
	tglx@linutronix.de, peterz@infradead.org,
	alexander.shishkin@linux.intel.com, robh@kernel.org,
	suzuki.poulose@arm.com, pawel.moll@arm.com,
	mathieu.poirier@linaro.org, mingo@redhat.com,
	linux-kernel@vger.kernel.org, Will Deacon <will.deacon@arm.com>
Subject: [PATCH 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2
Date: Fri, 27 Jan 2017 18:07:43 +0000	[thread overview]
Message-ID: <1485540470-11469-5-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1485540470-11469-1-git-send-email-will.deacon@arm.com>

The SPE architecture requires each exception level to enable access
to the SPE controls for the exception level below it, since additional
context-switch logic may be required to handle the buffer safely.

This patch allows EL1 (host) access to the SPE controls when entered at
EL2.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/kernel/head.S | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 4b1abac3485a..7f625d2e8e45 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -592,15 +592,26 @@ CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
 #endif
 
 	/* EL2 debug */
-	mrs	x0, id_aa64dfr0_el1		// Check ID_AA64DFR0_EL1 PMUVer
-	sbfx	x0, x0, #8, #4
+	mrs	x1, id_aa64dfr0_el1		// Check ID_AA64DFR0_EL1 PMUVer
+	sbfx	x0, x1, #8, #4
 	cmp	x0, #1
 	b.lt	4f				// Skip if no PMU present
 	mrs	x0, pmcr_el0			// Disable debug access traps
 	ubfx	x0, x0, #11, #5			// to EL2 and allow access to
 4:
-	csel	x0, xzr, x0, lt			// all PMU counters from EL1
-	msr	mdcr_el2, x0			// (if they exist)
+	csel	x3, xzr, x0, lt			// all PMU counters from EL1
+
+	/* Statistical profiling */
+	ubfx	x0, x1, #32, #4			// Check ID_AA64DFR0_EL1 PMSVer
+	cbz	x0, 6f				// Skip if SPE not present
+	cbnz	x2, 5f				// VHE?
+	mov	x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
+	orr	x3, x3, x1			// If we don't have VHE, then
+	b	6f				// use EL1&0 translation.
+5:						// For VHE, use EL2 translation
+	orr	x3, x3, #MDCR_EL2_TPMS		// and disable access from EL1
+6:
+	msr	mdcr_el2, x3			// Configure debug traps
 
 	/* Stage-2 translation */
 	msr	vttbr_el2, xzr
-- 
2.1.4

WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2
Date: Fri, 27 Jan 2017 18:07:43 +0000	[thread overview]
Message-ID: <1485540470-11469-5-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1485540470-11469-1-git-send-email-will.deacon@arm.com>

The SPE architecture requires each exception level to enable access
to the SPE controls for the exception level below it, since additional
context-switch logic may be required to handle the buffer safely.

This patch allows EL1 (host) access to the SPE controls when entered at
EL2.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/kernel/head.S | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 4b1abac3485a..7f625d2e8e45 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -592,15 +592,26 @@ CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
 #endif
 
 	/* EL2 debug */
-	mrs	x0, id_aa64dfr0_el1		// Check ID_AA64DFR0_EL1 PMUVer
-	sbfx	x0, x0, #8, #4
+	mrs	x1, id_aa64dfr0_el1		// Check ID_AA64DFR0_EL1 PMUVer
+	sbfx	x0, x1, #8, #4
 	cmp	x0, #1
 	b.lt	4f				// Skip if no PMU present
 	mrs	x0, pmcr_el0			// Disable debug access traps
 	ubfx	x0, x0, #11, #5			// to EL2 and allow access to
 4:
-	csel	x0, xzr, x0, lt			// all PMU counters from EL1
-	msr	mdcr_el2, x0			// (if they exist)
+	csel	x3, xzr, x0, lt			// all PMU counters from EL1
+
+	/* Statistical profiling */
+	ubfx	x0, x1, #32, #4			// Check ID_AA64DFR0_EL1 PMSVer
+	cbz	x0, 6f				// Skip if SPE not present
+	cbnz	x2, 5f				// VHE?
+	mov	x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
+	orr	x3, x3, x1			// If we don't have VHE, then
+	b	6f				// use EL1&0 translation.
+5:						// For VHE, use EL2 translation
+	orr	x3, x3, #MDCR_EL2_TPMS		// and disable access from EL1
+6:
+	msr	mdcr_el2, x3			// Configure debug traps
 
 	/* Stage-2 translation */
 	msr	vttbr_el2, xzr
-- 
2.1.4

  parent reply	other threads:[~2017-01-27 18:08 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-27 18:07 [PATCH 00/10] Add support for the ARMv8.2 Statistical Profiling Extension Will Deacon
2017-01-27 18:07 ` Will Deacon
2017-01-27 18:07 ` [PATCH 01/10] arm64: cpufeature: allow for version discrepancy in PMU implementations Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-01-27 18:07 ` [PATCH 02/10] arm64: cpufeature: Don't enforce system-wide SPE capability Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-01-27 18:07 ` [PATCH 03/10] arm64: KVM: Save/restore the host SPE state when entering/leaving a VM Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-02-01 16:29   ` Marc Zyngier
2017-02-01 16:29     ` Marc Zyngier
2017-02-02 18:18     ` Will Deacon
2017-02-02 18:18       ` Will Deacon
2017-02-02 18:21       ` Marc Zyngier
2017-02-02 18:21         ` Marc Zyngier
2017-01-27 18:07 ` Will Deacon [this message]
2017-01-27 18:07   ` [PATCH 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 Will Deacon
2017-02-01 16:22   ` Marc Zyngier
2017-02-01 16:22     ` Marc Zyngier
2017-02-09 18:26   ` Mark Rutland
2017-02-09 18:26     ` Mark Rutland
2017-01-27 18:07 ` [PATCH 05/10] genirq: export irq_get_percpu_devid_partition to modules Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-01-27 18:07 ` [PATCH 06/10] perf/core: Export AUX buffer helpers " Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-01-27 18:07 ` [PATCH 07/10] perf: Directly pass PERF_AUX_* flags to perf_aux_output_end Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-02-17 13:40   ` Alexander Shishkin
2017-02-17 13:40     ` Alexander Shishkin
2017-02-17 14:00     ` Will Deacon
2017-02-17 14:00       ` Will Deacon
2017-02-17 14:06       ` Alexander Shishkin
2017-02-17 14:06         ` Alexander Shishkin
2017-02-17 14:42         ` Will Deacon
2017-02-17 14:42           ` Will Deacon
2017-02-17 14:59           ` Alexander Shishkin
2017-02-17 14:59             ` Alexander Shishkin
2017-01-27 18:07 ` [PATCH 08/10] perf/core: Add PERF_AUX_FLAG_COLLISION to report colliding samples Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-03-31 16:44   ` Robin Murphy
2017-03-31 16:44     ` Robin Murphy
2017-01-27 18:07 ` [PATCH 09/10] drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension Will Deacon
2017-01-27 18:07   ` Will Deacon
2017-01-30 19:03   ` Kim Phillips
2017-01-30 19:03     ` Kim Phillips
2017-01-27 18:07 ` [PATCH 10/10] dt-bindings: Document devicetree binding for ARM SPE Will Deacon
2017-01-27 18:07   ` Will Deacon

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