From: Lina Iyer <lina.iyer@linaro.org> To: ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, Juri.Lelli@arm.com, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, brendan.jackman@arm.com, sudeep.holla@arm.com, andy.gross@linaro.org, Lina Iyer <lina.iyer@linaro.org> Subject: [PATCH V5 5/6] dt/bindings: Update binding for hierarchical PSCI states Date: Fri, 3 Mar 2017 13:48:16 -0800 [thread overview] Message-ID: <1488577697-127445-6-git-send-email-lina.iyer@linaro.org> (raw) In-Reply-To: <1488577697-127445-1-git-send-email-lina.iyer@linaro.org> Update device bindings to represent hierarchical CPU and CPU domain idle states. Also update the examples to clearly show how flattened and hierarchical states can be represented in DT. Cc: <devicetree@vger.kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> --- Documentation/devicetree/bindings/arm/psci.txt | 156 +++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d..e0e9281 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,163 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +PSCI v1.0 onwards, supports OS-Initiated mode for powering off CPU domains +from the firmware. Such PM domains for which the PSCI firmware driver acts as +pseudo-controller, may also be specified in the DT under the psci node. The +domain definitions must follow the domain idle state specifications per [3]. +The domain states themselves must be compatible with 'domain-idle-state' +defined in [1] and need to specify the arm,psci-suspend-param property for +each idle state. + +DT allows representing CPU and CPU cluster idle states in two different ways - + +The flattened model as given in Example 1, lists CPU's idle states followed by +the domain idle state that the CPUs may choose. This is the general practice +followed in PSCI firmwares that support Platform Coordinated mode. Note that +the idle states are all compatible with "arm,idle-state". + +Example 2 represents the hierarchical model of CPU and domain idle states. +CPUs define their domain provider in their DT node. The domain controls the +power to the CPU and possibly other h/w blocks that would be powered off when +the CPU is powered off. The CPU's idle states may therefore be considered as +the domain's idle states and have the compatible "arm,idle-state". Such +domains may be embedded within another domain that represents common h/w +blocks between these CPUs viz., the cluster. The idle states of the cluster +would be represented as the domain's idle states. In order to use OS-Initiated +mode of PSCI in the firmware, the hierarchial representation must be used. + +More information on defining CPU PM domains is available in [4]. + +Example 1: Flattened representation of CPU and domain idle states + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWR_DWN>; + }; + + idle-states { + CPU_PWRDN: cpu_power_down{ + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: domain_ret { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: domain_off { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +Example 2: Hierarchical representation of CPU and domain idle states + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + }; + + idle-states { + CPU_PWRDN: cpu_power_down{ + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: domain_ret { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: domain_off { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd@0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd@1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd@0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWR_DWN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt +[4]. CPU PM Domains description + Documentation/power/cpu_domains.txt -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: lina.iyer@linaro.org (Lina Iyer) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V5 5/6] dt/bindings: Update binding for hierarchical PSCI states Date: Fri, 3 Mar 2017 13:48:16 -0800 [thread overview] Message-ID: <1488577697-127445-6-git-send-email-lina.iyer@linaro.org> (raw) In-Reply-To: <1488577697-127445-1-git-send-email-lina.iyer@linaro.org> Update device bindings to represent hierarchical CPU and CPU domain idle states. Also update the examples to clearly show how flattened and hierarchical states can be represented in DT. Cc: <devicetree@vger.kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> --- Documentation/devicetree/bindings/arm/psci.txt | 156 +++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d..e0e9281 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,163 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +PSCI v1.0 onwards, supports OS-Initiated mode for powering off CPU domains +from the firmware. Such PM domains for which the PSCI firmware driver acts as +pseudo-controller, may also be specified in the DT under the psci node. The +domain definitions must follow the domain idle state specifications per [3]. +The domain states themselves must be compatible with 'domain-idle-state' +defined in [1] and need to specify the arm,psci-suspend-param property for +each idle state. + +DT allows representing CPU and CPU cluster idle states in two different ways - + +The flattened model as given in Example 1, lists CPU's idle states followed by +the domain idle state that the CPUs may choose. This is the general practice +followed in PSCI firmwares that support Platform Coordinated mode. Note that +the idle states are all compatible with "arm,idle-state". + +Example 2 represents the hierarchical model of CPU and domain idle states. +CPUs define their domain provider in their DT node. The domain controls the +power to the CPU and possibly other h/w blocks that would be powered off when +the CPU is powered off. The CPU's idle states may therefore be considered as +the domain's idle states and have the compatible "arm,idle-state". Such +domains may be embedded within another domain that represents common h/w +blocks between these CPUs viz., the cluster. The idle states of the cluster +would be represented as the domain's idle states. In order to use OS-Initiated +mode of PSCI in the firmware, the hierarchial representation must be used. + +More information on defining CPU PM domains is available in [4]. + +Example 1: Flattened representation of CPU and domain idle states + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWR_DWN>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWR_DWN>; + }; + + idle-states { + CPU_PWRDN: cpu_power_down{ + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: domain_ret { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: domain_off { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +Example 2: Hierarchical representation of CPU and domain idle states + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + }; + + idle-states { + CPU_PWRDN: cpu_power_down{ + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: domain_ret { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: domain_off { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd at 0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd at 1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd at 0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWR_DWN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt +[4]. CPU PM Domains description + Documentation/power/cpu_domains.txt -- 2.7.4
next prev parent reply other threads:[~2017-03-03 21:48 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-03 21:48 [PATCH V5 0/6] PSCI: Support hierarchical PM domains Lina Iyer 2017-03-03 21:48 ` Lina Iyer 2017-03-03 21:48 ` [PATCH V5 1/6] drivers: cpuidle: Read CPU's idle state from PM domain Lina Iyer 2017-03-03 21:48 ` Lina Iyer 2017-03-13 13:58 ` Brendan Jackman 2017-03-13 13:58 ` Brendan Jackman 2017-03-03 21:48 ` [PATCH V5 2/6] drivers: firmware: psci: Allow OS Initiated suspend mode Lina Iyer 2017-03-03 21:48 ` Lina Iyer 2017-03-03 21:48 ` [PATCH V5 3/6] drivers: firmware: psci: Support cluster idle states for OS-Initiated Lina Iyer 2017-03-03 21:48 ` Lina Iyer 2017-03-03 21:48 ` [PATCH V5 4/6] drivers: firmwware: psci: Support hierachical idle states Lina Iyer 2017-03-03 21:48 ` Lina Iyer 2017-03-03 21:48 ` Lina Iyer [this message] 2017-03-03 21:48 ` [PATCH V5 5/6] dt/bindings: Update binding for hierarchical PSCI states Lina Iyer 2017-03-03 21:48 ` [PATCH V5 6/6] ARM64: dts: Define CPU power domain for MSM8916 Lina Iyer 2017-03-03 21:48 ` Lina Iyer
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