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From: Chris Zhong <zyw@rock-chips.com>
To: linux-rockchip@lists.infradead.org
Cc: Chris Zhong <zyw@rock-chips.com>,
	Mark Yao <mark.yao@rock-chips.com>,
	David Airlie <airlied@linux.ie>, Heiko Stuebner <heiko@sntech.de>,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 2/3] drm/rockchip/dsi: enable the grf clk before writing grf registers
Date: Wed, 15 Mar 2017 16:42:31 +0800	[thread overview]
Message-ID: <1489567352-3333-2-git-send-email-zyw@rock-chips.com> (raw)
In-Reply-To: <1489567352-3333-1-git-send-email-zyw@rock-chips.com>

For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index f84f9ae..d8f24f2 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -291,6 +291,7 @@ struct dw_mipi_dsi {
 	struct regmap *grf_regmap;
 	void __iomem *base;
 
+	struct clk *grf_clk;
 	struct clk *pllref_clk;
 	struct clk *pclk;
 	struct clk *phy_cfg_clk;
@@ -979,6 +980,16 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	dw_mipi_dsi_dphy_interface_config(dsi);
 	dw_mipi_dsi_clear_err(dsi);
 
+	/*
+	 * For the RK3399, the clk of grf must be enabled before writing grf
+	 * register.
+	 */
+	ret = clk_prepare_enable(dsi->grf_clk);
+	if (ret) {
+		dev_err(dsi->dev, "Failed to enable grf_clk\n");
+		return;
+	}
+
 	if (pdata->grf_dsi0_mode_reg)
 		regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 			     pdata->grf_dsi0_mode);
@@ -1003,6 +1014,8 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 	dsi->dpms_mode = DRM_MODE_DPMS_ON;
+
+	clk_disable_unprepare(dsi->grf_clk);
 }
 
 static int
@@ -1238,6 +1251,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 		dev_dbg(dev, "have not phy_cfg_clk\n");
 	}
 
+	dsi->grf_clk = devm_clk_get(dev, "grf");
+	if (IS_ERR(dsi->grf_clk)) {
+		ret = PTR_ERR(dsi->grf_clk);
+		if (ret != -ENOENT) {
+			dev_err(dev, "Unable to get grf_clk: %d\n", ret);
+			return ret;
+		}
+		dsi->grf_clk = NULL;
+		dev_dbg(dev, "have not grf_clk\n");
+	}
+
 	ret = clk_prepare_enable(dsi->pllref_clk);
 	if (ret) {
 		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
-- 
2.6.3

WARNING: multiple messages have this Message-ID (diff)
From: Chris Zhong <zyw@rock-chips.com>
To: linux-rockchip@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Chris Zhong <zyw@rock-chips.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] drm/rockchip/dsi: enable the grf clk before writing grf registers
Date: Wed, 15 Mar 2017 16:42:31 +0800	[thread overview]
Message-ID: <1489567352-3333-2-git-send-email-zyw@rock-chips.com> (raw)
In-Reply-To: <1489567352-3333-1-git-send-email-zyw@rock-chips.com>

For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index f84f9ae..d8f24f2 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -291,6 +291,7 @@ struct dw_mipi_dsi {
 	struct regmap *grf_regmap;
 	void __iomem *base;
 
+	struct clk *grf_clk;
 	struct clk *pllref_clk;
 	struct clk *pclk;
 	struct clk *phy_cfg_clk;
@@ -979,6 +980,16 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	dw_mipi_dsi_dphy_interface_config(dsi);
 	dw_mipi_dsi_clear_err(dsi);
 
+	/*
+	 * For the RK3399, the clk of grf must be enabled before writing grf
+	 * register.
+	 */
+	ret = clk_prepare_enable(dsi->grf_clk);
+	if (ret) {
+		dev_err(dsi->dev, "Failed to enable grf_clk\n");
+		return;
+	}
+
 	if (pdata->grf_dsi0_mode_reg)
 		regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 			     pdata->grf_dsi0_mode);
@@ -1003,6 +1014,8 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 	dsi->dpms_mode = DRM_MODE_DPMS_ON;
+
+	clk_disable_unprepare(dsi->grf_clk);
 }
 
 static int
@@ -1238,6 +1251,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 		dev_dbg(dev, "have not phy_cfg_clk\n");
 	}
 
+	dsi->grf_clk = devm_clk_get(dev, "grf");
+	if (IS_ERR(dsi->grf_clk)) {
+		ret = PTR_ERR(dsi->grf_clk);
+		if (ret != -ENOENT) {
+			dev_err(dev, "Unable to get grf_clk: %d\n", ret);
+			return ret;
+		}
+		dsi->grf_clk = NULL;
+		dev_dbg(dev, "have not grf_clk\n");
+	}
+
 	ret = clk_prepare_enable(dsi->pllref_clk);
 	if (ret) {
 		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
-- 
2.6.3

_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: zyw@rock-chips.com (Chris Zhong)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] drm/rockchip/dsi: enable the grf clk before writing grf registers
Date: Wed, 15 Mar 2017 16:42:31 +0800	[thread overview]
Message-ID: <1489567352-3333-2-git-send-email-zyw@rock-chips.com> (raw)
In-Reply-To: <1489567352-3333-1-git-send-email-zyw@rock-chips.com>

For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index f84f9ae..d8f24f2 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -291,6 +291,7 @@ struct dw_mipi_dsi {
 	struct regmap *grf_regmap;
 	void __iomem *base;
 
+	struct clk *grf_clk;
 	struct clk *pllref_clk;
 	struct clk *pclk;
 	struct clk *phy_cfg_clk;
@@ -979,6 +980,16 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	dw_mipi_dsi_dphy_interface_config(dsi);
 	dw_mipi_dsi_clear_err(dsi);
 
+	/*
+	 * For the RK3399, the clk of grf must be enabled before writing grf
+	 * register.
+	 */
+	ret = clk_prepare_enable(dsi->grf_clk);
+	if (ret) {
+		dev_err(dsi->dev, "Failed to enable grf_clk\n");
+		return;
+	}
+
 	if (pdata->grf_dsi0_mode_reg)
 		regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 			     pdata->grf_dsi0_mode);
@@ -1003,6 +1014,8 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 	dsi->dpms_mode = DRM_MODE_DPMS_ON;
+
+	clk_disable_unprepare(dsi->grf_clk);
 }
 
 static int
@@ -1238,6 +1251,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 		dev_dbg(dev, "have not phy_cfg_clk\n");
 	}
 
+	dsi->grf_clk = devm_clk_get(dev, "grf");
+	if (IS_ERR(dsi->grf_clk)) {
+		ret = PTR_ERR(dsi->grf_clk);
+		if (ret != -ENOENT) {
+			dev_err(dev, "Unable to get grf_clk: %d\n", ret);
+			return ret;
+		}
+		dsi->grf_clk = NULL;
+		dev_dbg(dev, "have not grf_clk\n");
+	}
+
 	ret = clk_prepare_enable(dsi->pllref_clk);
 	if (ret) {
 		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
-- 
2.6.3

  reply	other threads:[~2017-03-15  8:43 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-15  8:42 [PATCH 1/3] dt-bindings: add the grf clock for dw-mipi-dsi Chris Zhong
2017-03-15  8:42 ` Chris Zhong
2017-03-15  8:42 ` Chris Zhong
2017-03-15  8:42 ` Chris Zhong [this message]
2017-03-15  8:42   ` [PATCH 2/3] drm/rockchip/dsi: enable the grf clk before writing grf registers Chris Zhong
2017-03-15  8:42   ` Chris Zhong
2017-03-15 16:47   ` Brian Norris
2017-03-15 16:47     ` Brian Norris
2017-03-15 16:47     ` Brian Norris
2017-03-15 16:55     ` John Keeping
2017-03-15 16:55       ` John Keeping
2017-03-15 16:55       ` John Keeping
2017-03-15  8:42 ` [PATCH 3/3] drm/rockchip/dsi: correct the grf_switch_reg name Chris Zhong
2017-03-15  8:42   ` Chris Zhong
2017-03-15  8:42   ` Chris Zhong
2017-03-15  9:03 ` [PATCH 1/3] dt-bindings: add the grf clock for dw-mipi-dsi Heiko Stübner
2017-03-15  9:03   ` Heiko Stübner
2017-03-15  9:03   ` Heiko Stübner
2017-03-15  9:55   ` Chris Zhong
2017-03-15  9:55     ` Chris Zhong
2017-03-15  9:55     ` Chris Zhong
2017-03-15 10:10     ` Heiko Stübner
2017-03-15 10:10       ` Heiko Stübner
2017-03-15 10:10       ` Heiko Stübner

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