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From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Felipe Balbi <felipe.balbi@linux.intel.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-usb@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>
Subject: [PATCH v5 2/9] phy: phy-mt65xx-usb3: increase LFPS filter threshold
Date: Fri, 31 Mar 2017 15:35:28 +0800	[thread overview]
Message-ID: <1490945735-9531-2-git-send-email-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <1490945735-9531-1-git-send-email-chunfeng.yun@mediatek.com>

Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/phy-mt65xx-usb3.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index fe2392a..4fd47d0 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -106,6 +106,10 @@
 #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)	((0x3 & (x)) << 10)
 
+#define U3P_U3_PHYD_LFPS1		(SSUSB_SIFSLV_U3PHYD_BASE + 0x000c)
+#define P3D_RG_FWAKE_TH		GENMASK(21, 16)
+#define P3D_RG_FWAKE_TH_VAL(x)	((0x3f & (x)) << 16)
+
 #define U3P_PHYD_CDR1		(SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
 #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
 #define P3D_RG_CDR_BIR_LTD1_VAL(x)	((0x1f & (x)) << 24)
@@ -303,6 +307,11 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
 	tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
 	writel(tmp, port_base + U3P_PHYD_CDR1);
 
+	tmp = readl(port_base + U3P_U3_PHYD_LFPS1);
+	tmp &= ~P3D_RG_FWAKE_TH;
+	tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
+	writel(tmp, port_base + U3P_U3_PHYD_LFPS1);
+
 	tmp = readl(port_base + U3P_U3_PHYD_RXDET1);
 	tmp &= ~P3D_RG_RXDET_STB2_SET;
 	tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)
From: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
To: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
Cc: Matthias Brugger
	<matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Felipe Balbi
	<felipe.balbi-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Ian Campbell
	<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
	Chunfeng Yun
	<chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v5 2/9] phy: phy-mt65xx-usb3: increase LFPS filter threshold
Date: Fri, 31 Mar 2017 15:35:28 +0800	[thread overview]
Message-ID: <1490945735-9531-2-git-send-email-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <1490945735-9531-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.

Signed-off-by: Chunfeng Yun <chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 drivers/phy/phy-mt65xx-usb3.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index fe2392a..4fd47d0 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -106,6 +106,10 @@
 #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)	((0x3 & (x)) << 10)
 
+#define U3P_U3_PHYD_LFPS1		(SSUSB_SIFSLV_U3PHYD_BASE + 0x000c)
+#define P3D_RG_FWAKE_TH		GENMASK(21, 16)
+#define P3D_RG_FWAKE_TH_VAL(x)	((0x3f & (x)) << 16)
+
 #define U3P_PHYD_CDR1		(SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
 #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
 #define P3D_RG_CDR_BIR_LTD1_VAL(x)	((0x1f & (x)) << 24)
@@ -303,6 +307,11 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
 	tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
 	writel(tmp, port_base + U3P_PHYD_CDR1);
 
+	tmp = readl(port_base + U3P_U3_PHYD_LFPS1);
+	tmp &= ~P3D_RG_FWAKE_TH;
+	tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
+	writel(tmp, port_base + U3P_U3_PHYD_LFPS1);
+
 	tmp = readl(port_base + U3P_U3_PHYD_RXDET1);
 	tmp &= ~P3D_RG_RXDET_STB2_SET;
 	tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
-- 
1.7.9.5

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WARNING: multiple messages have this Message-ID (diff)
From: chunfeng.yun@mediatek.com (Chunfeng Yun)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/9] phy: phy-mt65xx-usb3: increase LFPS filter threshold
Date: Fri, 31 Mar 2017 15:35:28 +0800	[thread overview]
Message-ID: <1490945735-9531-2-git-send-email-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <1490945735-9531-1-git-send-email-chunfeng.yun@mediatek.com>

Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/phy-mt65xx-usb3.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index fe2392a..4fd47d0 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -106,6 +106,10 @@
 #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)	((0x3 & (x)) << 10)
 
+#define U3P_U3_PHYD_LFPS1		(SSUSB_SIFSLV_U3PHYD_BASE + 0x000c)
+#define P3D_RG_FWAKE_TH		GENMASK(21, 16)
+#define P3D_RG_FWAKE_TH_VAL(x)	((0x3f & (x)) << 16)
+
 #define U3P_PHYD_CDR1		(SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
 #define P3D_RG_CDR_BIR_LTD1		GENMASK(28, 24)
 #define P3D_RG_CDR_BIR_LTD1_VAL(x)	((0x1f & (x)) << 24)
@@ -303,6 +307,11 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
 	tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
 	writel(tmp, port_base + U3P_PHYD_CDR1);
 
+	tmp = readl(port_base + U3P_U3_PHYD_LFPS1);
+	tmp &= ~P3D_RG_FWAKE_TH;
+	tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
+	writel(tmp, port_base + U3P_U3_PHYD_LFPS1);
+
 	tmp = readl(port_base + U3P_U3_PHYD_RXDET1);
 	tmp &= ~P3D_RG_RXDET_STB2_SET;
 	tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
-- 
1.7.9.5

  reply	other threads:[~2017-03-31  7:36 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-31  7:35 [PATCH v5 1/9] phy: phy-mt65xx-usb3: improve RX detection stable time Chunfeng Yun
2017-03-31  7:35 ` Chunfeng Yun
2017-03-31  7:35 ` Chunfeng Yun
2017-03-31  7:35 ` Chunfeng Yun [this message]
2017-03-31  7:35   ` [PATCH v5 2/9] phy: phy-mt65xx-usb3: increase LFPS filter threshold Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 3/9] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 4/9] phy: phy-mt65xx-usb3: move clock from phy node into port nodes Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 5/9] phy: phy-mt65xx-usb3: add support for new version phy Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 6/9] phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 7/9] arm64: dts: mt8173: split usb SuperSpeed port into two ports Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 8/9] arm64: dts: mt8173: move clock from phy node into port nodes Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35 ` [PATCH v5 9/9] dt-bindings: phy-mt65xx-usb: add support for new version phy Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-03-31  7:35   ` Chunfeng Yun
2017-04-06 10:28 ` [PATCH v5 1/9] phy: phy-mt65xx-usb3: improve RX detection stable time Kishon Vijay Abraham I
2017-04-06 10:28   ` Kishon Vijay Abraham I
2017-04-06 10:28   ` Kishon Vijay Abraham I
2017-04-06 10:49   ` Chunfeng Yun
2017-04-06 10:49     ` Chunfeng Yun
2017-04-06 10:49     ` Chunfeng Yun
2017-05-10  9:48   ` Matthias Brugger
2017-05-10  9:48     ` Matthias Brugger
2017-05-10  9:48     ` Matthias Brugger

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