From: Sylwester Nawrocki <s.nawrocki@samsung.com> To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org Cc: javier@osg.samsung.com, b.zolnierkie@samsung.com, sw0312.kim@samsung.com, krzk@kernel.org, cw00.choi@samsung.com, broonie@kernel.org, Sylwester Nawrocki <s.nawrocki@samsung.com>, robh+dt@kernel.org Subject: [PATCH RFC 3/7] clk: samsung: exynos542x: Add EPLL rate table Date: Fri, 21 Apr 2017 19:19:47 +0200 [thread overview] Message-ID: <1492795191-31298-4-git-send-email-s.nawrocki@samsung.com> (raw) In-Reply-To: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> A specific clock rate table is added for EPLL so it is possible to set frequency of the EPLL output clock as multiple of various audio sampling rates. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 87c711a..6fbd6ae 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1279,6 +1279,22 @@ static void __init exynos5420_clk_sleep_init(void) {} PLL_35XX_RATE(200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { + PLL_36XX_RATE(600000000U, 100, 2, 1, 0), + PLL_36XX_RATE(400000000U, 200, 2, 2, 0), + PLL_36XX_RATE(393216000U, 197, 3, 2, 25690), + PLL_36XX_RATE(361267200U, 301, 5, 2, 3671), + PLL_36XX_RATE(200000000U, 200, 3, 3, 0), + PLL_36XX_RATE(196608000U, 197, 3, 3, -25690), + PLL_36XX_RATE(180633600U, 301, 5, 3, 3671), + PLL_36XX_RATE(131072000U, 131, 3, 3, 4719), + PLL_36XX_RATE(100000000U, 200, 3, 4, 0), + PLL_36XX_RATE( 65536000U, 131, 3, 4, 4719), + PLL_36XX_RATE( 49152000U, 197, 3, 5, 25690), + PLL_36XX_RATE( 45158400U, 301, 5, 3, 3671), + PLL_36XX_RATE( 32768000U, 131, 3, 5, 4719), +}; + static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), @@ -1286,7 +1302,7 @@ static void __init exynos5420_clk_sleep_init(void) {} CPLL_CON0, NULL), [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, DPLL_CON0, NULL), - [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, + [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, NULL), [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, RPLL_CON0, NULL), @@ -1401,7 +1417,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } -- 1.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
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From: Sylwester Nawrocki <s.nawrocki@samsung.com> To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org Cc: inki.dae@samsung.com, sw0312.kim@samsung.com, cw00.choi@samsung.com, javier@osg.samsung.com, krzk@kernel.org, jy0922.shim@samsung.com, broonie@kernel.org, robh+dt@kernel.org, b.zolnierkie@samsung.com, Sylwester Nawrocki <s.nawrocki@samsung.com> Subject: [PATCH RFC 3/7] clk: samsung: exynos542x: Add EPLL rate table Date: Fri, 21 Apr 2017 19:19:47 +0200 [thread overview] Message-ID: <1492795191-31298-4-git-send-email-s.nawrocki@samsung.com> (raw) In-Reply-To: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> A specific clock rate table is added for EPLL so it is possible to set frequency of the EPLL output clock as multiple of various audio sampling rates. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 87c711a..6fbd6ae 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1279,6 +1279,22 @@ static void __init exynos5420_clk_sleep_init(void) {} PLL_35XX_RATE(200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { + PLL_36XX_RATE(600000000U, 100, 2, 1, 0), + PLL_36XX_RATE(400000000U, 200, 2, 2, 0), + PLL_36XX_RATE(393216000U, 197, 3, 2, 25690), + PLL_36XX_RATE(361267200U, 301, 5, 2, 3671), + PLL_36XX_RATE(200000000U, 200, 3, 3, 0), + PLL_36XX_RATE(196608000U, 197, 3, 3, -25690), + PLL_36XX_RATE(180633600U, 301, 5, 3, 3671), + PLL_36XX_RATE(131072000U, 131, 3, 3, 4719), + PLL_36XX_RATE(100000000U, 200, 3, 4, 0), + PLL_36XX_RATE( 65536000U, 131, 3, 4, 4719), + PLL_36XX_RATE( 49152000U, 197, 3, 5, 25690), + PLL_36XX_RATE( 45158400U, 301, 5, 3, 3671), + PLL_36XX_RATE( 32768000U, 131, 3, 5, 4719), +}; + static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), @@ -1286,7 +1302,7 @@ static void __init exynos5420_clk_sleep_init(void) {} CPLL_CON0, NULL), [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, DPLL_CON0, NULL), - [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, + [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, NULL), [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, RPLL_CON0, NULL), @@ -1401,7 +1417,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } -- 1.9.1
next prev parent reply other threads:[~2017-04-21 17:19 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20170421172007epcas1p25dba753df34c309e6b00ed08ae930043@epcas1p2.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 0/7] HDMI audio support for Exynos Odroid boards Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki [not found] ` <CGME20170421172016epcas5p342c16e1219c1205a44a84eaa770ad5ac@epcas5p3.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 1/7] clk: samsung: Add enable/disable operation for PLL36XX clocks Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki 2017-04-22 2:51 ` Stephen Boyd 2017-04-24 11:12 ` Sylwester Nawrocki 2017-04-24 11:12 ` Sylwester Nawrocki 2017-04-22 15:22 ` Krzysztof Kozlowski 2017-04-24 11:12 ` Sylwester Nawrocki 2017-04-24 11:12 ` Sylwester Nawrocki 2017-04-24 11:18 ` Krzysztof Kozlowski 2017-04-24 11:18 ` Krzysztof Kozlowski 2017-04-24 11:35 ` Sylwester Nawrocki 2017-04-24 11:50 ` Krzysztof Kozlowski [not found] ` <CGME20170421172023epcas1p3dd7397c8c61daa548ffac88a76e53113@epcas1p3.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 2/7] clk: samsung: Add definitions of some audio related clocks Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki 2017-04-22 15:27 ` Krzysztof Kozlowski 2017-06-08 10:00 ` Sylwester Nawrocki [not found] ` <CGME20170421172029epcas5p1b32ed135c5e0f1b86fbcc54279126349@epcas5p1.samsung.com> 2017-04-21 17:19 ` Sylwester Nawrocki [this message] 2017-04-21 17:19 ` [PATCH RFC 3/7] clk: samsung: exynos542x: Add EPLL rate table Sylwester Nawrocki 2017-04-22 15:28 ` Krzysztof Kozlowski [not found] ` <CGME20170421172034epcas5p1dafc1794a7649ec30053f7f62d1831e5@epcas5p1.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 4/7] drm: exynos: Add driver for HDMI audio interface Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki 2017-04-22 15:31 ` Krzysztof Kozlowski [not found] ` <CGME20170421172040epcas5p2ee7191a899c52ea3f077837dc2e865ca@epcas5p2.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 5/7] ASoC: Add Odroid sound DT bindings documentation Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki 2017-04-21 17:28 ` Applied "ASoC: Add Odroid sound DT bindings documentation" to the asoc tree Mark Brown 2017-04-21 17:28 ` Mark Brown 2017-04-21 17:31 ` Krzysztof Kozlowski 2017-04-21 17:31 ` Krzysztof Kozlowski 2017-04-21 17:58 ` Mark Brown 2017-04-21 17:58 ` Mark Brown 2017-04-21 18:01 ` Krzysztof Kozlowski 2017-04-21 18:01 ` Krzysztof Kozlowski 2017-04-21 18:07 ` Krzysztof Kozlowski 2017-04-21 18:07 ` Krzysztof Kozlowski 2017-04-24 9:57 ` Mark Brown 2017-04-28 17:03 ` [PATCH RFC 5/7] ASoC: Add Odroid sound DT bindings documentation Rob Herring 2017-06-09 16:53 ` Sylwester Nawrocki [not found] ` <CGME20170421172046epcas1p32778006ff0ddc30083d49b31497b5b5b@epcas1p3.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 6/7] ASoC: samsung: Add Odroid ASoC machine driver Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki 2017-04-21 17:28 ` Applied "ASoC: samsung: Add Odroid ASoC machine driver" to the asoc tree Mark Brown 2017-04-21 17:28 ` Mark Brown [not found] ` <CGME20170421172053epcas1p26cbba167969b1bffb48e3b7e6f5c3604@epcas1p2.samsung.com> 2017-04-21 17:19 ` [PATCH RFC 7/7] ARM: dts: samsung: Switch to dedicated Odroid sound card binding Sylwester Nawrocki 2017-04-21 17:19 ` Sylwester Nawrocki 2017-04-21 18:43 ` Krzysztof Kozlowski
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