[Qemu-devel] [PULL v1 03/17] target-microblaze: Don't hard code 0xb as initial MB version

From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistai@xilinx.com, sai.pavan.boddu@xilinx.com,
	edgar.iglesias@xilinx.com
Subject: [Qemu-devel] [PULL v1 03/17] target-microblaze: Don't hard code 0xb as initial MB version
Date: Tue,  4 Jul 2017 11:54:34 +0200	[thread overview]
Message-ID: <1499162088-1562-4-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1499162088-1562-1-git-send-email-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Don't hard code 0xb as initial MB version.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index af70faa..4bc77df 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -152,8 +152,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \
                        | PVR0_USE_ICACHE_MASK \
-                       | PVR0_USE_DCACHE_MASK \
-                       | (0xb << 8);
+                       | PVR0_USE_DCACHE_MASK;
     env->pvr.regs[2] = PVR2_D_OPB_MASK \
                         | PVR2_D_LMB_MASK \
                         | PVR2_I_OPB_MASK \
-- 
2.7.4
