From: Shawn Guo <shawnguo@kernel.org> To: Thierry Reding <thierry.reding@gmail.com> Cc: Baoyou Xie <xie.baoyou@sanechips.com.cn>, Xin Zhou <zhou.xin8@sanechips.com.cn>, Jun Nie <jun.nie@linaro.org>, linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo <shawn.guo@linaro.org> Subject: [PATCH v2 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller Date: Thu, 27 Jul 2017 16:23:36 +0800 [thread overview] Message-ID: <1501143817-15843-2-git-send-email-shawnguo@kernel.org> (raw) In-Reply-To: <1501143817-15843-1-git-send-email-shawnguo@kernel.org> From: Shawn Guo <shawn.guo@linaro.org> It adds bindings document for ZTE ZX PWM controller. The device has two clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the reference clock for calculating period and duty cycles. Also, the device supports polarity configuration, so #pwm-cells should be 3. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm@1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + }; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: shawnguo@kernel.org (Shawn Guo) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller Date: Thu, 27 Jul 2017 16:23:36 +0800 [thread overview] Message-ID: <1501143817-15843-2-git-send-email-shawnguo@kernel.org> (raw) In-Reply-To: <1501143817-15843-1-git-send-email-shawnguo@kernel.org> From: Shawn Guo <shawn.guo@linaro.org> It adds bindings document for ZTE ZX PWM controller. The device has two clocks: PCLK and WCLK. The PCLK is for register access, and WCLK is the reference clock for calculating period and duty cycles. Also, the device supports polarity configuration, so #pwm-cells should be 3. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/pwm/pwm-zx.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-zx.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-zx.txt b/Documentation/devicetree/bindings/pwm/pwm-zx.txt new file mode 100644 index 000000000000..a6bcc75c9164 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-zx.txt @@ -0,0 +1,22 @@ +ZTE ZX PWM controller + +Required properties: + - compatible: Should be "zte,zx296718-pwm". + - reg: Physical base address and length of the controller's registers. + - clocks : The phandle and specifier referencing the controller's clocks. + - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The + PCLK is for register access, while WCLK is the reference clock for + calculating period and duty cycles. + - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Example: + + pwm: pwm at 1439000 { + compatible = "zte,zx296718-pwm"; + reg = <0x1439000 0x1000>; + clocks = <&lsp1crm LSP1_PWM_PCLK>, + <&lsp1crm LSP1_PWM_WCLK>; + clock-names = "pclk", "wclk"; + #pwm-cells = <3>; + }; -- 1.9.1
next prev parent reply other threads:[~2017-07-27 8:24 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-07-27 8:23 [PATCH v2 0/2] Add ZTE ZX PWM device driver support Shawn Guo 2017-07-27 8:23 ` Shawn Guo 2017-07-27 8:23 ` Shawn Guo [this message] 2017-07-27 8:23 ` [PATCH v2 1/2] dt-bindings: pwm: add bindings doc for ZTE ZX PWM controller Shawn Guo 2017-08-21 5:50 ` Thierry Reding 2017-08-21 5:50 ` Thierry Reding 2017-07-27 8:23 ` [PATCH v2 2/2] pwm: add ZTE ZX PWM device driver Shawn Guo 2017-07-27 8:23 ` Shawn Guo 2017-08-21 6:03 ` Thierry Reding 2017-08-21 6:03 ` Thierry Reding 2017-08-22 8:23 ` Shawn Guo 2017-08-22 8:23 ` Shawn Guo 2017-08-18 12:50 ` [PATCH v2 0/2] Add ZTE ZX PWM device driver support Shawn Guo 2017-08-18 12:50 ` Shawn Guo
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