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From: Fabrice Gasnier <fabrice.gasnier@st.com>
To: <jic23@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <mcoquelin.stm32@gmail.com>,
	<alexandre.torgue@st.com>, <fabrice.gasnier@st.com>,
	<benjamin.gaignard@st.com>, <benjamin.gaignard@linaro.org>,
	<linux-iio@vger.kernel.org>, <lars@metafoo.de>, <knaack.h@gmx.de>,
	<pmeerw@pmeerw.net>
Subject: [PATCH 1/3] iio: trigger: stm32-timer: preset shouldn't be buffered
Date: Mon, 18 Sep 2017 12:05:30 +0200	[thread overview]
Message-ID: <1505729132-1369-2-git-send-email-fabrice.gasnier@st.com> (raw)
In-Reply-To: <1505729132-1369-1-git-send-email-fabrice.gasnier@st.com>

Currently, setting preset value (ARR) will update directly 'Auto reload
value' only on 1st write access. But then, ARPE is set. This makes
ARR a shadow register. Preset value should be updated upon each
write request: ensure ARPE is 0. This fixes successive writes to
preset attribute.

Fixes: 4adec7da0536 ("iio: stm32 trigger: Add quadrature encoder device")

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
---
 drivers/iio/trigger/stm32-timer-trigger.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c
index 9b90534..34cc25b 100644
--- a/drivers/iio/trigger/stm32-timer-trigger.c
+++ b/drivers/iio/trigger/stm32-timer-trigger.c
@@ -715,8 +715,9 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
 	if (ret)
 		return ret;
 
+	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
+	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 	regmap_write(priv->regmap, TIM_ARR, preset);
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 
 	return len;
 }
-- 
1.9.1

WARNING: multiple messages have this Message-ID (diff)
From: fabrice.gasnier@st.com (Fabrice Gasnier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] iio: trigger: stm32-timer: preset shouldn't be buffered
Date: Mon, 18 Sep 2017 12:05:30 +0200	[thread overview]
Message-ID: <1505729132-1369-2-git-send-email-fabrice.gasnier@st.com> (raw)
In-Reply-To: <1505729132-1369-1-git-send-email-fabrice.gasnier@st.com>

Currently, setting preset value (ARR) will update directly 'Auto reload
value' only on 1st write access. But then, ARPE is set. This makes
ARR a shadow register. Preset value should be updated upon each
write request: ensure ARPE is 0. This fixes successive writes to
preset attribute.

Fixes: 4adec7da0536 ("iio: stm32 trigger: Add quadrature encoder device")

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
---
 drivers/iio/trigger/stm32-timer-trigger.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c
index 9b90534..34cc25b 100644
--- a/drivers/iio/trigger/stm32-timer-trigger.c
+++ b/drivers/iio/trigger/stm32-timer-trigger.c
@@ -715,8 +715,9 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
 	if (ret)
 		return ret;
 
+	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
+	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 	regmap_write(priv->regmap, TIM_ARR, preset);
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 
 	return len;
 }
-- 
1.9.1

  reply	other threads:[~2017-09-18 10:06 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-18 10:05 [PATCH 0/3] iio: trigger: stm32-timers fixes Fabrice Gasnier
2017-09-18 10:05 ` Fabrice Gasnier
2017-09-18 10:05 ` Fabrice Gasnier [this message]
2017-09-18 10:05   ` [PATCH 1/3] iio: trigger: stm32-timer: preset shouldn't be buffered Fabrice Gasnier
2017-09-24 12:09   ` Jonathan Cameron
2017-09-24 12:09     ` Jonathan Cameron
2017-09-18 10:05 ` [PATCH 2/3] iio: trigger: stm32-timer: fix a corner case to write preset Fabrice Gasnier
2017-09-18 10:05   ` Fabrice Gasnier
2017-09-24 12:10   ` Jonathan Cameron
2017-09-24 12:10     ` Jonathan Cameron
2017-09-18 10:05 ` [PATCH 3/3] iio: trigger: stm32-timer: enable clock when in master mode Fabrice Gasnier
2017-09-18 10:05   ` Fabrice Gasnier
2017-09-24 12:22   ` Jonathan Cameron
2017-09-24 12:22     ` Jonathan Cameron

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