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From: David Wu <david.wu@rock-chips.com>
To: heiko@sntech.de, linus.walleij@linaro.org
Cc: huangtao@rock-chips.com, andy.yan@rock-chips.com,
	linux-rockchip@lists.infradead.org, linux-gpio@vger.kernel.org,
	linux-kernel@vger.kernel.org, David Wu <david.wu@rock-chips.com>
Subject: [PATCH 1/2] pinctrl: rockchip: Fix the rk3399 gpio0 and gpio1 banks' drv_offset at pmu grf
Date: Sat, 30 Sep 2017 20:13:20 +0800	[thread overview]
Message-ID: <1506773601-27315-2-git-send-email-david.wu@rock-chips.com> (raw)
In-Reply-To: <1506773601-27315-1-git-send-email-david.wu@rock-chips.com>

The offset of gpio0 and gpio1 bank drive strength is 0x8, not 0x4.
But the mux is 0x4, we couldn't use the IOMUX_WIDTH_4BIT flag, so
we give them actual offset.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/pinctrl/pinctrl-rockchip.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index b5cb785..c7c9beb 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3456,8 +3456,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
 							 DRV_TYPE_IO_1V8_ONLY,
 							 DRV_TYPE_IO_DEFAULT,
 							 DRV_TYPE_IO_DEFAULT,
-							 0x0,
-							 0x8,
+							 0x80,
+							 0x88,
 							 -1,
 							 -1,
 							 PULL_TYPE_IO_1V8_ONLY,
@@ -3473,10 +3473,10 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
 					DRV_TYPE_IO_1V8_OR_3V0,
 					DRV_TYPE_IO_1V8_OR_3V0,
 					DRV_TYPE_IO_1V8_OR_3V0,
-					0x20,
-					0x28,
-					0x30,
-					0x38
+					0xa0,
+					0xa8,
+					0xb0,
+					0xb8
 					),
 	PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
 				      DRV_TYPE_IO_1V8_OR_3V0,
-- 
1.9.1



  reply	other threads:[~2017-09-30 12:13 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-30 12:13 [PATCH 0/2] Fix two pinctrl issues David Wu
2017-09-30 12:13 ` David Wu [this message]
2017-09-30 12:13 ` [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii David Wu
2017-09-30 15:07   ` Heiko Stuebner
2017-10-07 10:32     ` Linus Walleij
2017-10-07 18:50       ` Heiko Stuebner
2017-10-09  1:21       ` David.Wu

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