[PATCH v13 01/21] drm/i915/guc: Add GuC submission initialization/enable state variables

[Sagar Arun Kamble <sagar.a.kamble@intel.com>]

In order to reduce the dependency on enable_guc_submission parameter
we are adding GuC submission status variables, submission_initialized
and submission_enabled to track the initialization/enable status.
i915_guc_submission_initialized and i915_guc_submission_enabled need
to be used at places needing the check.

v2: Added status variables instead of depending on stage_desc_pool
and execbuf_client. (Joonas, Chris) Replaced other usages of
enable_guc_submission with i915_guc_submission_enabled check. It is
important to note that this status based enable/disable helps identify
paths that are not sanitizing properly like in reset/unload currently.
Future patches in the series will fix that sanitization.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c            |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c    |  2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/i915_irq.c            |  2 +-
 drivers/gpu/drm/i915/intel_guc.h           | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_guc_loader.c    | 10 +++++-----
 drivers/gpu/drm/i915/intel_guc_log.c       | 10 +++++-----
 drivers/gpu/drm/i915/intel_lrc.c           |  2 +-
 drivers/gpu/drm/i915/intel_uc.c            | 23 +++++++++++++----------
 9 files changed, 59 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 66fc156..8e25846 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -374,7 +374,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
 
 			if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
 			    i915_modparams.enable_execlists &&
-			    !i915_modparams.enable_guc_submission)
+			    !i915_guc_submission_enabled(&dev_priv->guc))
 				value |= I915_SCHEDULER_CAP_PREEMPTION;
 		}
 		break;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..f7c24c0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -407,7 +407,7 @@ struct i915_gem_context *
 	i915_gem_context_set_closed(ctx); /* not user accessible */
 	i915_gem_context_clear_bannable(ctx);
 	i915_gem_context_set_force_single_submission(ctx);
-	if (!i915_modparams.enable_guc_submission)
+	if (!i915_guc_submission_enabled(&ctx->i915->guc))
 		ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
 
 	GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index f15de4d..3da1346 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -975,7 +975,7 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
 	void *vaddr;
 	int ret;
 
-	if (guc->stage_desc_pool)
+	if (i915_guc_submission_initialized(guc))
 		return 0;
 
 	vma = intel_guc_allocate_vma(guc,
@@ -1004,6 +1004,8 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
 
 	ida_init(&guc->stage_ids);
 
+	guc->submission_initialized = true;
+
 	return 0;
 
 err_log:
@@ -1019,11 +1021,16 @@ void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
 
+	if (!i915_guc_submission_initialized(guc))
+		return;
+
 	ida_destroy(&guc->stage_ids);
 	guc_ads_destroy(guc);
 	intel_guc_log_destroy(guc);
 	i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
 	i915_vma_unpin_and_release(&guc->stage_desc_pool);
+
+	guc->submission_initialized = false;
 }
 
 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
@@ -1100,6 +1107,9 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 	int err;
 
+	if (i915_guc_submission_enabled(guc))
+		return 0;
+
 	/*
 	 * We're using GuC work items for submitting work through GuC. Since
 	 * we're coalescing multiple requests from a single context into a
@@ -1151,6 +1161,8 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
 		tasklet_schedule(&execlists->irq_tasklet);
 	}
 
+	guc->submission_enabled = true;
+
 	return 0;
 
 err_execbuf_client:
@@ -1163,6 +1175,9 @@ void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
 
+	if (!i915_guc_submission_enabled(guc))
+		return;
+
 	guc_interrupts_release(dev_priv);
 
 	/* Revert back to manual ELSP submission */
@@ -1170,4 +1185,6 @@ void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
 
 	guc_client_free(guc->execbuf_client);
 	guc->execbuf_client = NULL;
+
+	guc->submission_enabled = false;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3736290..a3de408 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1388,7 +1388,7 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
 
 	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
 		notify_ring(engine);
-		tasklet |= i915_modparams.enable_guc_submission;
+		tasklet |= i915_guc_submission_enabled(&engine->i915->guc);
 	}
 
 	if (tasklet)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index aa9a7b5..5046264f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -44,6 +44,10 @@ struct intel_guc {
 	/* intel_guc_recv interrupt related state */
 	bool interrupts_enabled;
 
+	/* GuC submission related state */
+	bool submission_initialized;
+	bool submission_enabled;
+
 	struct i915_vma *ads_vma;
 	struct i915_vma *stage_desc_pool;
 	void *stage_desc_pool_vaddr;
@@ -93,6 +97,16 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 	return offset;
 }
 
+static inline bool i915_guc_submission_initialized(struct intel_guc *guc)
+{
+	return guc->submission_initialized;
+}
+
+static inline bool i915_guc_submission_enabled(struct intel_guc *guc)
+{
+	return guc->submission_enabled;
+}
+
 void intel_guc_init_early(struct intel_guc *guc);
 void intel_guc_init_send_regs(struct intel_guc *guc);
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index c7a800a..5449e5e 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -137,8 +137,10 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
 	} else
 		params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 
-	/* If GuC submission is enabled, set up additional parameters here */
-	if (i915_modparams.enable_guc_submission) {
+	/*
+	 * If GuC submission is initialized, set up additional parameters here.
+	 */
+	if (i915_guc_submission_initialized(guc)) {
 		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
 		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
@@ -367,9 +369,7 @@ int intel_guc_init_hw(struct intel_guc *guc)
 
 	guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
 
-	DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
-		 i915_modparams.enable_guc_submission ? "submission enabled" :
-							"loaded",
+	DRM_INFO("GuC loaded (firmware %s [version %u.%u])\n",
 		 guc->fw.path,
 		 guc->fw.major_ver_found, guc->fw.minor_ver_found);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 76d3eb1..0f201c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,8 +505,8 @@ static void guc_flush_logs(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
-	if (!i915_modparams.enable_guc_submission ||
-	    (i915_modparams.guc_log_level < 0))
+	if (!i915_guc_submission_enabled(guc) ||
+	    i915_modparams.guc_log_level < 0)
 		return;
 
 	/* First disable the interrupts, will be renabled afterwards */
@@ -646,8 +646,8 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 
 void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-	if (!i915_modparams.enable_guc_submission ||
-	    (i915_modparams.guc_log_level < 0))
+	if (!i915_guc_submission_enabled(&dev_priv->guc) ||
+	    i915_modparams.guc_log_level < 0)
 		return;
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
@@ -657,7 +657,7 @@ void i915_guc_log_register(struct drm_i915_private *dev_priv)
 
 void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-	if (!i915_modparams.enable_guc_submission)
+	if (!i915_guc_submission_enabled(&dev_priv->guc))
 		return;
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fbfcf88..e9c3454 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1462,7 +1462,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
 	execlists->preempt = false;
 
 	/* After a GPU reset, we may have requests to replay */
-	if (!i915_modparams.enable_guc_submission && execlists->first)
+	if (!i915_guc_submission_enabled(&dev_priv->guc) && execlists->first)
 		tasklet_schedule(&execlists->irq_tasklet);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 7b938e8..b33d469 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -212,11 +212,15 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		goto err_log_capture;
 
 	intel_huc_auth(&dev_priv->huc);
-	if (i915_modparams.enable_guc_submission) {
+	if (i915_guc_submission_initialized(guc)) {
 		if (i915_modparams.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
 
 		ret = i915_guc_submission_enable(dev_priv);
+
+		DRM_INFO("GuC submission %s\n",
+			 i915_guc_submission_enabled(guc) ?
+			 "enabled" : "disabled");
 		if (ret)
 			goto err_interrupts;
 	}
@@ -238,8 +242,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 err_log_capture:
 	guc_capture_load_err_log(guc);
 err_submission:
-	if (i915_modparams.enable_guc_submission)
-		i915_guc_submission_fini(dev_priv);
+	i915_guc_submission_fini(dev_priv);
 err_guc:
 	i915_ggtt_disable_guc(dev_priv);
 
@@ -263,20 +266,20 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 {
-	guc_free_load_err_log(&dev_priv->guc);
+	struct intel_guc *guc = &dev_priv->guc;
+
+	guc_free_load_err_log(guc);
 
 	if (!i915_modparams.enable_guc_loading)
 		return;
 
-	if (i915_modparams.enable_guc_submission)
-		i915_guc_submission_disable(dev_priv);
+	i915_guc_submission_disable(dev_priv);
 
-	guc_disable_communication(&dev_priv->guc);
+	guc_disable_communication(guc);
 
-	if (i915_modparams.enable_guc_submission) {
+	if (i915_guc_submission_enabled(guc))
 		gen9_disable_guc_interrupts(dev_priv);
-		i915_guc_submission_fini(dev_priv);
-	}
+	i915_guc_submission_fini(dev_priv);
 
 	i915_ggtt_disable_guc(dev_priv);
 }
-- 
1.9.1

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