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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 3/5] arm: check regime, not current state, for ATS write PAR format
Date: Mon, 20 Nov 2017 17:37:22 +0000	[thread overview]
Message-ID: <1511199444-17922-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org>

In do_ats_write(), rather than using extended_addresses_enabled() to
decide whether the value we get back from get_phys_addr() is a 64-bit
format PAR or a 32-bit one, use arm_s1_regime_using_lpae_format().

This is not really the correct answer, because the PAR format
depends on the AT instruction being used, not just on the
translation regime. However getting this correct requires a
significant refactoring, so that get_phys_addr() returns raw
information about the fault which the caller can then assemble
into a suitable FSR/PAR/syndrome for its purposes, rather than
get_phys_addr() returning a pre-formatted FSR.

However this change at least improves the situation by making
the PAR work correctly for address translation operations done
at AArch64 EL2 on the EL2 translation regime. In particular,
this is necessary for Xen to be able to run in our emulation,
so this seems like a safer interim fix given that we are in freeze.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Stefano Stabellini <sstabellini@kernel.org>
Message-id: 1509719814-6191-1-git-send-email-peter.maydell@linaro.org
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 35c5bd6..91a9300 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2169,7 +2169,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
 
     ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
                         &prot, &page_size, &fsr, &fi, &cacheattrs);
-    if (extended_addresses_enabled(env)) {
+    if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
         /* fsr is a DFSR/IFSR value for the long descriptor
          * translation table format, but with WnR always clear.
          * Convert it to a 64-bit PAR.
-- 
2.7.4

  parent reply	other threads:[~2017-11-20 17:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-20 17:37 [Qemu-devel] [PULL 0/5] target-arm queue for rc2 Peter Maydell
2017-11-20 17:37 ` [Qemu-devel] [PULL 1/5] target/arm: Report GICv3 sysregs present in ID registers if needed Peter Maydell
2017-11-20 17:37 ` [Qemu-devel] [PULL 2/5] nvic: Fix ARMv7M MPU_RBAR reads Peter Maydell
2017-11-20 17:37 ` Peter Maydell [this message]
2017-11-20 17:37 ` [Qemu-devel] [PULL 4/5] hw/arm/aspeed: Unlock SCU when running kernel Peter Maydell
2017-11-20 17:37 ` [Qemu-devel] [PULL 5/5] hw/arm: Silence xlnx-ep108 deprecation warning during tests Peter Maydell
2017-11-21 10:44 ` [Qemu-devel] [PULL 0/5] target-arm queue for rc2 Peter Maydell

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