From: clinton.a.taylor@intel.com
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915: Register definitions for DP Phy compiance
Date: Thu, 1 Mar 2018 11:36:12 -0800 [thread overview]
Message-ID: <1519932972-7785-1-git-send-email-clinton.a.taylor@intel.com> (raw)
From: Clint Taylor <clinton.a.taylor@intel.com>
DisplayPort Phy compliance test patterns register definitions.
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51..91152c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8702,6 +8702,24 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x640F0
+#define DDI_DP_COMP_CTL_B 0x641F0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x640f4
+#define DDI_DP_COMP_PAT_B 0x641f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, DDI_DP_COMP_PAT_B) + (i) * 4) /* 3 dwords */
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
1.9.1
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next reply other threads:[~2018-03-01 19:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-01 19:36 clinton.a.taylor [this message]
2018-03-01 19:57 ` ✓ Fi.CI.BAT: success for drm/i915: Register definitions for DP Phy compiance Patchwork
2018-03-02 2:56 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-02 18:10 ` [PATCH] " Rodrigo Vivi
2018-03-02 18:51 ` Clint Taylor
2018-03-04 22:39 ` Jani Nikula
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