From: Lin Huang <hl@rock-chips.com> To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, dbasehore@chromium.org, diander@chromium.org, briannorris@chromium.org, shawn.lin@rock-chips.com, Lin Huang <hl@rock-chips.com> Subject: [PATCH v2 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Date: Fri, 16 Mar 2018 11:02:27 +0800 [thread overview] Message-ID: <1521169348-8552-1-git-send-email-hl@rock-chips.com> (raw) Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, and these two PLL may change their frequency. If we do not assign right id to pclk_ddr and hclk_sd, they will alway use default cur register value, and may get the frequency exceed their signed off frequency. So assign correct Id for them, then we can assign frequency for them in dts. Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v2: - add more detail in commit message drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 3e57c6e..bca10d6 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(9), 7, GFLAGS, &rk3399_uart3_fracmux), - COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, + COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(3), 4, GFLAGS), @@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(31), 8, GFLAGS), /* sdio & sdmmc */ - COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, + COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(12), 13, GFLAGS), GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org> To: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org, briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, diander-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH v2 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Date: Fri, 16 Mar 2018 11:02:27 +0800 [thread overview] Message-ID: <1521169348-8552-1-git-send-email-hl@rock-chips.com> (raw) Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, and these two PLL may change their frequency. If we do not assign right id to pclk_ddr and hclk_sd, they will alway use default cur register value, and may get the frequency exceed their signed off frequency. So assign correct Id for them, then we can assign frequency for them in dts. Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v2: - add more detail in commit message drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 3e57c6e..bca10d6 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(9), 7, GFLAGS, &rk3399_uart3_fracmux), - COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, + COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(3), 4, GFLAGS), @@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(31), 8, GFLAGS), /* sdio & sdmmc */ - COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, + COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(12), 13, GFLAGS), GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, -- 2.7.4
next reply other threads:[~2018-03-16 3:02 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-16 3:02 Lin Huang [this message] 2018-03-16 3:02 ` [PATCH v2 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Lin Huang 2018-03-16 3:02 ` [PATCH v2 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock Lin Huang 2018-03-16 3:02 ` Lin Huang 2018-03-16 17:16 ` Doug Anderson 2018-03-16 17:16 ` Doug Anderson
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