From: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> To: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>, Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Simon Xue <xxm-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Subject: [PATCH v5 09/10] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller Date: Mon, 2 Apr 2018 09:04:14 +0800 [thread overview] Message-ID: <1522631054-151768-1-git-send-email-shawn.lin@rock-chips.com> (raw) In-Reply-To: <1522630865-151344-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> This patch documents the DT bindings for the Rockchip PCIe controller when configured in endpoint mode. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- .../devicetree/bindings/pci/rockchip-pcie-ep.txt | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt new file mode 100644 index 0000000..77846730 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt @@ -0,0 +1,62 @@ +* Rockchip AXI PCIe Endpoint Controller DT description + +Required properties: +- compatible: Should contain "rockchip,rk3399-pcie-ep" +- reg: Two register ranges as listed in the reg-names property +- reg-names: Must include the following names + - "apb-base" + - "mem-base" +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "aclk" + - "aclk-perf" + - "hclk" + - "pm" +- resets: Must contain seven entries for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following names + - "core" + - "mgmt" + - "mgmt-sticky" + - "pipe" + - "pm" + - "aclk" + - "pclk" +- pinctrl-names : The pin control state names +- pinctrl-0: The "default" pinctrl state +- phys: Must contain an phandle to a PHY for each entry in phy-names. +- phy-names: Must include 4 entries for all 4 lanes even if some of + them won't be used for your cases. Entries are of the form "pcie-phy-N": + where N ranges from 0 to 3. + (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt + for changing the #phy-cells of phy node to support it) +- rockchip,max-outbound-regions: Maximum number of outbound regions + +Optional Property: +- num-lanes: number of lanes to use +- max-functions: Maximum number of functions that can be configured (default 1). + +pcie0-ep: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + #address-cells = <3>; + #size-cells = <2>; + rockchip,max-outbound-regions = <16>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; + reg-names = "apb-base", "mem-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq>; +}; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Lin <shawn.lin@rock-chips.com> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <bhelgaas@google.com> Cc: Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>, Jeffy Chen <jeffy.chen@rock-chips.com>, Simon Xue <xxm@rock-chips.com>, linux-pci@vger.kernel.org, Shawn Lin <shawn.lin@rock-chips.com> Subject: [PATCH v5 09/10] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller Date: Mon, 2 Apr 2018 09:04:14 +0800 [thread overview] Message-ID: <1522631054-151768-1-git-send-email-shawn.lin@rock-chips.com> (raw) In-Reply-To: <1522630865-151344-1-git-send-email-shawn.lin@rock-chips.com> This patch documents the DT bindings for the Rockchip PCIe controller when configured in endpoint mode. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/pci/rockchip-pcie-ep.txt | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt new file mode 100644 index 0000000..77846730 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt @@ -0,0 +1,62 @@ +* Rockchip AXI PCIe Endpoint Controller DT description + +Required properties: +- compatible: Should contain "rockchip,rk3399-pcie-ep" +- reg: Two register ranges as listed in the reg-names property +- reg-names: Must include the following names + - "apb-base" + - "mem-base" +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "aclk" + - "aclk-perf" + - "hclk" + - "pm" +- resets: Must contain seven entries for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following names + - "core" + - "mgmt" + - "mgmt-sticky" + - "pipe" + - "pm" + - "aclk" + - "pclk" +- pinctrl-names : The pin control state names +- pinctrl-0: The "default" pinctrl state +- phys: Must contain an phandle to a PHY for each entry in phy-names. +- phy-names: Must include 4 entries for all 4 lanes even if some of + them won't be used for your cases. Entries are of the form "pcie-phy-N": + where N ranges from 0 to 3. + (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt + for changing the #phy-cells of phy node to support it) +- rockchip,max-outbound-regions: Maximum number of outbound regions + +Optional Property: +- num-lanes: number of lanes to use +- max-functions: Maximum number of functions that can be configured (default 1). + +pcie0-ep: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + #address-cells = <3>; + #size-cells = <2>; + rockchip,max-outbound-regions = <16>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; + reg-names = "apb-base", "mem-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq>; +}; -- 1.9.1
next prev parent reply other threads:[~2018-04-02 1:04 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-02 1:01 [PATCH v5 0/10] Add endpoint driver for Rockchip PCIe controller Shawn Lin 2018-04-02 1:01 ` Shawn Lin 2018-04-02 1:04 ` [PATCH v5 10/10] arm64: defconfig: update config for Rockchip PCIe Shawn Lin 2018-04-02 1:04 ` Shawn Lin 2018-04-02 1:04 ` Shawn Lin [not found] ` <1522630865-151344-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-04-02 1:01 ` [PATCH v5 01/10] PCI: Rename directory from host to controller Shawn Lin 2018-04-02 1:01 ` Shawn Lin [not found] ` <1522630910-151391-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-04-23 14:37 ` Lorenzo Pieralisi 2018-04-23 14:37 ` Lorenzo Pieralisi [not found] ` <20180423143727.GA17979-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2018-04-25 10:49 ` Lorenzo Pieralisi 2018-04-25 10:49 ` Lorenzo Pieralisi [not found] ` <20180425104917.GB15875-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2018-04-26 0:48 ` Shawn Lin 2018-04-26 0:48 ` Shawn Lin [not found] ` <ac1b92e0-7cfc-6cad-4113-cfd863ede572-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-04-26 17:05 ` Lorenzo Pieralisi 2018-04-26 17:05 ` Lorenzo Pieralisi [not found] ` <20180426170515.GA8928-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2018-04-27 2:50 ` Shawn Lin 2018-04-27 2:50 ` Shawn Lin 2018-04-02 1:02 ` [PATCH v5 02/10] PCI: cadence: Move cadence drivers back to controller directory Shawn Lin 2018-04-02 1:02 ` Shawn Lin 2018-04-02 1:02 ` [PATCH v5 03/10] PCI: dwc: Move dwc " Shawn Lin 2018-04-02 1:02 ` Shawn Lin 2018-04-02 1:02 ` [PATCH v5 04/10] PCI: rockchip: Factor out common code and host code Shawn Lin 2018-04-02 1:03 ` [PATCH v5 05/10] PCI: rockchip: Split out common function to parse DT Shawn Lin 2018-04-02 1:03 ` Shawn Lin 2018-04-02 1:03 ` [PATCH v5 06/10] PCI: rockchip: Split out common function to init controller Shawn Lin 2018-04-02 1:03 ` Shawn Lin 2018-04-02 1:03 ` [PATCH v5 07/10] dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt Shawn Lin 2018-04-02 1:03 ` Shawn Lin 2018-04-02 1:04 ` [PATCH v5 08/10] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller Shawn Lin 2018-04-02 1:04 ` Shawn Lin 2018-04-02 1:04 ` Shawn Lin [this message] 2018-04-02 1:04 ` [PATCH v5 09/10] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller Shawn Lin 2018-04-23 1:07 ` [PATCH v5 0/10] Add endpoint driver for Rockchip PCIe controller Shawn Lin 2018-04-23 1:07 ` Shawn Lin
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