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From: Michel Pollet <michel.pollet@bp.renesas.com>
To: linux-renesas-soc@vger.kernel.org, Simon Horman <horms@verge.net.au>
Cc: phil.edworthy@renesas.com,
	"Michel Pollet" <buserror+upstream@gmail.com>,
	"Michel Pollet" <michel.pollet@bp.renesas.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Magnus Damm" <magnus.damm@gmail.com>,
	"Russell King" <linux@armlinux.org.uk>,
	"Kevin Hilman" <khilman@baylibre.com>,
	"Andy Gross" <andy.gross@linaro.org>,
	"Maxime Ripard" <maxime.ripard@bootlin.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Carlo Caione" <carlo@endlessm.com>,
	"Frank Rowand" <frank.rowand@sony.com>,
	"Juri Lelli" <juri.lelli@arm.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: dts: Renesas RZ/N1D SMP enable method
Date: Tue, 17 Apr 2018 13:48:02 +0100	[thread overview]
Message-ID: <1523969291-41756-4-git-send-email-michel.pollet@bp.renesas.com> (raw)
In-Reply-To: <1523969291-41756-1-git-send-email-michel.pollet@bp.renesas.com>

Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 23c56d7..170376d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -33,6 +33,8 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <1>;
+			enable-method = "renesas,r9a06g032-smp";
+			cpu-release-addr = <0x4000c204>;
 		};
 	};
 
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: michel.pollet@bp.renesas.com (Michel Pollet)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: dts: Renesas RZ/N1D SMP enable method
Date: Tue, 17 Apr 2018 13:48:02 +0100	[thread overview]
Message-ID: <1523969291-41756-4-git-send-email-michel.pollet@bp.renesas.com> (raw)
In-Reply-To: <1523969291-41756-1-git-send-email-michel.pollet@bp.renesas.com>

Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 23c56d7..170376d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -33,6 +33,8 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <1>;
+			enable-method = "renesas,r9a06g032-smp";
+			cpu-release-addr = <0x4000c204>;
 		};
 	};
 
-- 
2.7.4

  parent reply	other threads:[~2018-04-17 12:53 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-17 12:47 [PATCH v2 0/3] Renesas RZ/N1D SMP enabler Michel Pollet
2018-04-17 12:47 ` Michel Pollet
2018-04-17 12:48 ` [PATCH v2 1/3] dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method Michel Pollet
2018-04-17 12:48   ` Michel Pollet
2018-04-17 12:48 ` [PATCH v2 2/3] arm: shmobile: Add the RZ/N1D SMP enabler driver Michel Pollet
2018-04-17 12:48   ` Michel Pollet
2018-04-17 12:48 ` Michel Pollet [this message]
2018-04-17 12:48   ` [PATCH v2 3/3] ARM: dts: Renesas RZ/N1D SMP enable method Michel Pollet

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