From: Vidya Srinivas <vidya.srinivas@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v6 2/6] drm/i915: Enable Display WA 0528
Date: Sat, 5 May 2018 13:06:05 +0000 (UTC)
Date: Sun, 6 May 2018 23:14:41 +0530 [thread overview]
Message-ID: <1525628685-24554-3-git-send-email-vidya.srinivas@intel.com> (raw)
In-Reply-To: <1525628685-24554-1-git-send-email-vidya.srinivas@intel.com>
From: "Srinivas, Vidya" <vidya.srinivas@intel.com>
Possible hang with NV12 plane surface formats.
WA: When the plane source pixel format is NV12,
the CHICKEN_PIPESL_* register bit 22 must be set to 1
and the render decompression must not be enabled
on any of the planes in that pipe.
v2: removed unnecessary POSTING_READ
v3: Added RB from Maarten
v4: Removed support for NV12 for BROXTON
Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 871347f..4279188 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -489,9 +489,21 @@ static const struct intel_limit intel_limits_bxt = {
};
static void
+skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
+{
+ if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+ return;
+
+ if (enable)
+ I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
+ else
+ I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
+}
+
+static void
skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
- if (IS_SKYLAKE(dev_priv))
+ if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
return;
if (enable)
@@ -5193,8 +5205,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
/* Display WA 827 */
if (needs_nv12_wa(dev_priv, old_crtc_state) &&
- !needs_nv12_wa(dev_priv, pipe_config))
+ !needs_nv12_wa(dev_priv, pipe_config)) {
skl_wa_clkgate(dev_priv, crtc->pipe, false);
+ skl_wa_528(dev_priv, crtc->pipe, false);
+ }
}
static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5231,8 +5245,10 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
/* Display WA 827 */
if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
- needs_nv12_wa(dev_priv, pipe_config))
+ needs_nv12_wa(dev_priv, pipe_config)) {
skl_wa_clkgate(dev_priv, crtc->pipe, true);
+ skl_wa_528(dev_priv, crtc->pipe, true);
+ }
/*
* Vblank time updates from the shadow to live plane control register
--
2.7.4
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next prev parent reply other threads:[~2018-05-05 13:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-05 13:06 [PATCH v6 0/6] Enable NV12 support Vidya Srinivas
2018-05-05 13:06 ` Vidya Srinivas [this message]
2018-05-05 13:06 ` [PATCH v6 1/6] drm/i915: Enable display workaround 827 for all planes, v2 Vidya Srinivas
2018-05-05 13:06 ` [PATCH v6 3/6] drm/i915: Add skl_check_nv12_surface for NV12 Vidya Srinivas
2018-05-05 13:06 ` [PATCH v6 6/6] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-05-07 8:07 ` Maarten Lankhorst
2018-05-07 8:11 ` Srinivas, Vidya
2018-05-07 8:13 ` Maarten Lankhorst
2018-05-07 8:16 ` Srinivas, Vidya
2018-05-07 8:20 ` Srinivas, Vidya
2018-05-07 8:25 ` Maarten Lankhorst
2018-05-07 8:29 ` Srinivas, Vidya
2018-05-07 8:28 ` Maarten Lankhorst
2018-05-07 8:34 ` Srinivas, Vidya
2018-05-07 8:38 ` Maarten Lankhorst
2018-05-07 8:41 ` Srinivas, Vidya
2018-05-05 13:06 ` [PATCH v6 4/6] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-05-05 13:06 ` [PATCH v6 5/6] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-05-05 13:28 ` ✗ Fi.CI.CHECKPATCH: warning for Enable NV12 support (rev4) Patchwork
2018-05-05 13:43 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-05 14:34 ` ✓ Fi.CI.IGT: " Patchwork
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