[PATCH v2 1/2] drm/i915: Use 64-bit to Read/Write fence reg on SNB+

[Zhao Yakui <yakui.zhao@intel.com>]

Based on HW spec the fence reg on SNB+ is defined as 64-bit. Just follow
the b-spec to  use 64-bit read/write mode.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d548ac0..d92fe03 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -63,6 +63,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
 	i915_reg_t fence_reg_lo, fence_reg_hi;
 	int fence_pitch_shift;
 	u64 val;
+	struct drm_i915_private *dev_priv = fence->i915;
 
 	if (INTEL_GEN(fence->i915) >= 6) {
 		fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
@@ -92,9 +93,14 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
 		val |= I965_FENCE_REG_VALID;
 	}
 
-	if (!pipelined) {
-		struct drm_i915_private *dev_priv = fence->i915;
+	if (INTEL_GEN(fence->i915) >= 6) {
+		/* Use the 64-bit RW to read/write fence reg on SNB+ */
+		I915_WRITE64_FW(fence_reg_lo, 0);
+		I915_READ64(fence_reg_lo);
 
+		I915_WRITE64_FW(fence_reg_lo, val);
+		I915_READ64(fence_reg_lo);
+	} else {
 		/* To w/a incoherency with non-atomic 64-bit register updates,
 		 * we split the 64-bit update into two 32-bit writes. In order
 		 * for a partial fence not to be evaluated between writes, we
-- 
2.7.4

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