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From: Damian Kos <dkos@cadence.com>
To: "David Airlie" <airlied@linux.ie>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Gustavo Padovan" <gustavo@padovan.org>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Sean Paul" <seanpaul@chromium.org>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Damian Kos" <dkos@cadence.com>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Cc: <ltyrala@cadence.com>, <pgaj@cadence.com>, <stelford@cadence.com>,
	"Quentin Schulz" <quentin.schulz@free-electrons.com>
Subject: [PATCH 07/12] drm/dp: fix drm_dp_link_train_clock_recovery_delay for DP 1.4
Date: Tue, 3 Jul 2018 11:02:18 +0100	[thread overview]
Message-ID: <1530612152-27555-8-git-send-email-dkos@cadence.com> (raw)
In-Reply-To: <1530612152-27555-1-git-send-email-dkos@cadence.com>

From: Quentin Schulz <quentin.schulz@free-electrons.com>

In DP 1.4, interval between link status and adjust request read for the
clock recovery phase is fixed to 100us whatever the value of the
register is.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Damian Kos <dkos@cadence.com>
---
 drivers/gpu/drm/drm_dp_helper.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index b6a27ab..92f3880 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -152,6 +152,11 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 	unsigned int training_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 		DP_TRAINING_AUX_RD_INTERVAL_MASK;
 
+	if (dpcd[DP_DPCD_REV] == 0x14) {
+		udelay(100);
+		return;
+	}
+
 	if (training_interval == 0)
 		udelay(100);
 	else
-- 
1.7.1


WARNING: multiple messages have this Message-ID (diff)
From: Damian Kos <dkos@cadence.com>
To: "David Airlie" <airlied@linux.ie>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Gustavo Padovan" <gustavo@padovan.org>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Sean Paul" <seanpaul@chromium.org>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Damian Kos" <dkos@cadence.com>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Cc: ltyrala@cadence.com, pgaj@cadence.com, stelford@cadence.com,
	Quentin Schulz <quentin.schulz@free-electrons.com>
Subject: [PATCH 07/12] drm/dp: fix drm_dp_link_train_clock_recovery_delay for DP 1.4
Date: Tue, 3 Jul 2018 11:02:18 +0100	[thread overview]
Message-ID: <1530612152-27555-8-git-send-email-dkos@cadence.com> (raw)
In-Reply-To: <1530612152-27555-1-git-send-email-dkos@cadence.com>

From: Quentin Schulz <quentin.schulz@free-electrons.com>

In DP 1.4, interval between link status and adjust request read for the
clock recovery phase is fixed to 100us whatever the value of the
register is.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Damian Kos <dkos@cadence.com>
---
 drivers/gpu/drm/drm_dp_helper.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index b6a27ab..92f3880 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -152,6 +152,11 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 	unsigned int training_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 		DP_TRAINING_AUX_RD_INTERVAL_MASK;
 
+	if (dpcd[DP_DPCD_REV] == 0x14) {
+		udelay(100);
+		return;
+	}
+
 	if (training_interval == 0)
 		udelay(100);
 	else
-- 
1.7.1

WARNING: multiple messages have this Message-ID (diff)
From: dkos@cadence.com (Damian Kos)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 07/12] drm/dp: fix drm_dp_link_train_clock_recovery_delay for DP 1.4
Date: Tue, 3 Jul 2018 11:02:18 +0100	[thread overview]
Message-ID: <1530612152-27555-8-git-send-email-dkos@cadence.com> (raw)
In-Reply-To: <1530612152-27555-1-git-send-email-dkos@cadence.com>

From: Quentin Schulz <quentin.schulz@free-electrons.com>

In DP 1.4, interval between link status and adjust request read for the
clock recovery phase is fixed to 100us whatever the value of the
register is.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Damian Kos <dkos@cadence.com>
---
 drivers/gpu/drm/drm_dp_helper.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index b6a27ab..92f3880 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -152,6 +152,11 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 	unsigned int training_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 		DP_TRAINING_AUX_RD_INTERVAL_MASK;
 
+	if (dpcd[DP_DPCD_REV] == 0x14) {
+		udelay(100);
+		return;
+	}
+
 	if (training_interval == 0)
 		udelay(100);
 	else
-- 
1.7.1

  parent reply	other threads:[~2018-07-03 10:03 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-03 10:02 [PATCH 00/12] drm: add support for Cadence MHDP DPI/DP bridge Damian Kos
2018-07-03 10:02 ` Damian Kos
2018-07-03 10:02 ` Damian Kos
2018-07-03 10:02 ` [PATCH 01/12] HACK: increase timeout for drm_atomic_helper_wait_for_vblanks Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 02/12] drm/dp: make dp_link_status and dp_get_lane_status usable from outside of the core Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 03/12] drm/dp: add helpers for drm_dp_set_adjust_request_pre_emphasis and drm_dp_set_adjust_request_voltage Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-04  8:16   ` Daniel Vetter
2018-07-04  8:16     ` Daniel Vetter
2018-07-04  8:16     ` Daniel Vetter
2018-07-03 10:02 ` [PATCH 04/12] drm/dp: fix training interval formula for DP 1.3+ Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 05/12] drm/dp: fix link probing for devices supporting DP 1.4+ Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 06/12] drm/dp: fix drm_dp_link_power_* for DP 1.2+ Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` Damian Kos [this message]
2018-07-03 10:02   ` [PATCH 07/12] drm/dp: fix drm_dp_link_train_clock_recovery_delay for DP 1.4 Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 08/12] drm/dp: add max number of lanes supported Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 09/12] drm/dp: add pixel encoding and colorimetry format indicator field in MISC1 Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 10/12] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-16 21:14   ` Rob Herring
2018-07-16 21:14     ` Rob Herring
2018-07-16 21:14     ` Rob Herring
2018-07-03 10:02 ` [PATCH 11/12] drm/rockchip: added implementation for a few FW commands Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02 ` [PATCH 12/12] drm/rockchip: add support for CDNS MHDP IP controller Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 10:02   ` Damian Kos
2018-07-03 11:03   ` Heiko Stübner
2018-07-03 11:03     ` Heiko Stübner
2018-07-03 11:03     ` Heiko Stübner
2018-07-03 14:06     ` Damian Kos
2018-07-03 14:06       ` Damian Kos
2018-07-03 14:06       ` Damian Kos
2018-07-03 14:06       ` Damian Kos

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