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From: Dinh Nguyen <dinguyen@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, marex@denx.de,
	yamada.masahiro@socionext.com, dinguyen@kernel.org,
	devicetree@vger.kernel.org, robh+dt@kernel.org
Subject: [PATCH 2/2] ARM: dts: socfpga: update NAND clocking for c5/a5
Date: Mon,  9 Jul 2018 17:41:03 -0500	[thread overview]
Message-ID: <1531176063-30140-2-git-send-email-dinguyen@kernel.org> (raw)
In-Reply-To: <1531176063-30140-1-git-send-email-dinguyen@kernel.org>

The nand_x_clk is derived from the nand_clk. Also, update the NAND dts property
with the correct clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/boot/dts/socfpga.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index b38f8c2..ae432b9 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -486,7 +486,7 @@
 					nand_clk: nand_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
-						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						clocks = <&nand_x_clk>;
 						clk-gate = <0xa0 10>;
 						fixed-divider = <4>;
 					};
@@ -754,7 +754,8 @@
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <0x0 0x90 0x4>;
 			dma-mask = <0xffffffff>;
-			clocks = <&nand_x_clk>;
+			clocks = <&nand_clk>, <&nand_x_clk>;
+			clock-names = "nand", "nand_x";
 			status = "disabled";
 		};
 
-- 
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: dinguyen@kernel.org (Dinh Nguyen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: socfpga: update NAND clocking for c5/a5
Date: Mon,  9 Jul 2018 17:41:03 -0500	[thread overview]
Message-ID: <1531176063-30140-2-git-send-email-dinguyen@kernel.org> (raw)
In-Reply-To: <1531176063-30140-1-git-send-email-dinguyen@kernel.org>

The nand_x_clk is derived from the nand_clk. Also, update the NAND dts property
with the correct clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/boot/dts/socfpga.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index b38f8c2..ae432b9 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -486,7 +486,7 @@
 					nand_clk: nand_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
-						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						clocks = <&nand_x_clk>;
 						clk-gate = <0xa0 10>;
 						fixed-divider = <4>;
 					};
@@ -754,7 +754,8 @@
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <0x0 0x90 0x4>;
 			dma-mask = <0xffffffff>;
-			clocks = <&nand_x_clk>;
+			clocks = <&nand_clk>, <&nand_x_clk>;
+			clock-names = "nand", "nand_x";
 			status = "disabled";
 		};
 
-- 
2.7.4

  reply	other threads:[~2018-07-09 22:41 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-09 22:41 [PATCH 1/2] ARM: dts: arria10: update NAND clocking Dinh Nguyen
2018-07-09 22:41 ` Dinh Nguyen
2018-07-09 22:41 ` Dinh Nguyen [this message]
2018-07-09 22:41   ` [PATCH 2/2] ARM: dts: socfpga: update NAND clocking for c5/a5 Dinh Nguyen
2018-07-10  1:31 ` [PATCH 1/2] ARM: dts: arria10: update NAND clocking Masahiro Yamada
2018-07-10  1:31   ` Masahiro Yamada
2018-07-10 13:35   ` Dinh Nguyen
2018-07-10 13:35     ` Dinh Nguyen
2018-07-11  2:43     ` Masahiro Yamada
2018-07-11  2:43       ` Masahiro Yamada
2018-07-11 14:51       ` Dinh Nguyen
2018-07-11 14:51         ` Dinh Nguyen
2018-07-19  2:22         ` Masahiro Yamada
2018-07-19  2:22           ` Masahiro Yamada
2018-07-20 23:16           ` Dinh Nguyen
2018-07-20 23:16             ` Dinh Nguyen
2018-07-23  1:48             ` Masahiro Yamada
2018-07-23  1:48               ` Masahiro Yamada

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