From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: cdall@kernel.org, kvm@vger.kernel.org, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, dave.martin@arm.com, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Subject: [PATCH v4 12/20] kvm: arm64: Dynamic configuration of VTTBR mask Date: Wed, 18 Jul 2018 10:18:55 +0100 [thread overview] Message-ID: <1531905547-25478-13-git-send-email-suzuki.poulose@arm.com> (raw) In-Reply-To: <1531905547-25478-1-git-send-email-suzuki.poulose@arm.com> On arm64 VTTBR_EL2:BADDR holds the base address for the stage2 translation table. The Arm ARM mandates that the bits BADDR[x-1:0] should be 0, where 'x' is defined for a given IPA Size and the number of levels for a translation granule size. It is defined using some magical constants. This patch is a reverse engineered implementation to calculate the 'x' at runtime for a given ipa and number of page table levels. See patch for more details. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <cdall@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Changes since V3: - Update reference to latest ARM ARM and improve commentary --- arch/arm64/include/asm/kvm_arm.h | 63 ++++++++++++++++++++++++++++++++++++---- arch/arm64/include/asm/kvm_mmu.h | 25 +++++++++++++++- 2 files changed, 81 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 87d2db6..66cf1df 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -122,7 +122,6 @@ #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) #define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT) #define VTCR_EL2_T0SZ_MASK 0x3f -#define VTCR_EL2_T0SZ_40B 24 #define VTCR_EL2_VS_SHIFT 19 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) @@ -139,11 +138,8 @@ * Note that when using 4K pages, we concatenate two first level page tables * together. With 16K pages, we concatenate 16 first level page tables. * - * The magic numbers used for VTTBR_X in this patch can be found in Tables - * D4-23 and D4-25 in ARM DDI 0487A.b. */ -#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) @@ -174,9 +170,64 @@ #endif #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) -#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) +/* + * ARM VMSAv8-64 defines an algorithm for finding the translation table + * descriptors in section D4.2.8 in ARM DDI 0487C.a. + * + * The algorithm defines the expectations on the BaseAddress (for the page + * table) bits resolved at each level based on the page size, entry level + * and T0SZ. The variable "x" in the algorithm also affects the VTTBR:BADDR + * for stage2 page table. + * + * The value of "x" is calculated as : + * x = Magic_N - T0SZ + * + * where Magic_N is an integer depending on the page size and the entry + * level of the page table as below: + * + * -------------------------------------------- + * | Entry level | 4K 16K 64K | + * -------------------------------------------- + * | Level: 0 (4 levels) | 28 | - | - | + * -------------------------------------------- + * | Level: 1 (3 levels) | 37 | 31 | 25 | + * -------------------------------------------- + * | Level: 2 (2 levels) | 46 | 42 | 38 | + * -------------------------------------------- + * | Level: 3 (1 level) | - | 53 | 51 | + * -------------------------------------------- + * + * We have a magic formula for the Magic_N below: + * + * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) + * + * where Number_of_levels = (4 - Level). We are only interested in the + * value for Entry_Level for the stage2 page table. + * + * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: + * + * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) + * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) + * + * Here is one way to explain the Magic Formula: + * + * x = log2(Size_of_Entry_Level_Table) + * + * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another + * PAGE_SHIFT bits in the PTE, we have : + * + * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) + * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 + * where n = number of levels, and since each pointer is 8bytes, we have: + * + * x = Bits_Entry_Level + 3 + * = IPA_SHIFT - (PAGE_SHIFT - 3) * n + * + * The only constraint here is that, we have to find the number of page table + * levels for a given IPA size (which we do, see stage2_pt_levels()) + */ +#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) -#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) #define VTTBR_VMID_SHIFT (UL(48)) #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index 6b36fc3..4f22772 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -145,7 +145,6 @@ static inline unsigned long __kern_hyp_va(unsigned long v) #define kvm_phys_shift(kvm) KVM_PHYS_SHIFT #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) -#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK static inline bool kvm_page_empty(void *ptr) { @@ -501,5 +500,29 @@ static inline int hyp_map_aux_data(void) #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) +/* + * Get the magic number 'x' for VTTBR:BADDR of this KVM instance. + * With v8.2 LVA extensions, 'x' should be a minimum of 6 with + * 52bit IPS. + */ +static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels) +{ + int x = ARM64_VTTBR_X(ipa_shift, levels); + + return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x; +} + +static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels) +{ + unsigned int x = arm64_vttbr_x(ipa_shift, levels); + + return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x); +} + +static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) +{ + return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)); +} + #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: suzuki.poulose@arm.com (Suzuki K Poulose) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 12/20] kvm: arm64: Dynamic configuration of VTTBR mask Date: Wed, 18 Jul 2018 10:18:55 +0100 [thread overview] Message-ID: <1531905547-25478-13-git-send-email-suzuki.poulose@arm.com> (raw) In-Reply-To: <1531905547-25478-1-git-send-email-suzuki.poulose@arm.com> On arm64 VTTBR_EL2:BADDR holds the base address for the stage2 translation table. The Arm ARM mandates that the bits BADDR[x-1:0] should be 0, where 'x' is defined for a given IPA Size and the number of levels for a translation granule size. It is defined using some magical constants. This patch is a reverse engineered implementation to calculate the 'x' at runtime for a given ipa and number of page table levels. See patch for more details. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <cdall@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Changes since V3: - Update reference to latest ARM ARM and improve commentary --- arch/arm64/include/asm/kvm_arm.h | 63 ++++++++++++++++++++++++++++++++++++---- arch/arm64/include/asm/kvm_mmu.h | 25 +++++++++++++++- 2 files changed, 81 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 87d2db6..66cf1df 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -122,7 +122,6 @@ #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) #define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT) #define VTCR_EL2_T0SZ_MASK 0x3f -#define VTCR_EL2_T0SZ_40B 24 #define VTCR_EL2_VS_SHIFT 19 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) @@ -139,11 +138,8 @@ * Note that when using 4K pages, we concatenate two first level page tables * together. With 16K pages, we concatenate 16 first level page tables. * - * The magic numbers used for VTTBR_X in this patch can be found in Tables - * D4-23 and D4-25 in ARM DDI 0487A.b. */ -#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) @@ -174,9 +170,64 @@ #endif #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) -#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) +/* + * ARM VMSAv8-64 defines an algorithm for finding the translation table + * descriptors in section D4.2.8 in ARM DDI 0487C.a. + * + * The algorithm defines the expectations on the BaseAddress (for the page + * table) bits resolved at each level based on the page size, entry level + * and T0SZ. The variable "x" in the algorithm also affects the VTTBR:BADDR + * for stage2 page table. + * + * The value of "x" is calculated as : + * x = Magic_N - T0SZ + * + * where Magic_N is an integer depending on the page size and the entry + * level of the page table as below: + * + * -------------------------------------------- + * | Entry level | 4K 16K 64K | + * -------------------------------------------- + * | Level: 0 (4 levels) | 28 | - | - | + * -------------------------------------------- + * | Level: 1 (3 levels) | 37 | 31 | 25 | + * -------------------------------------------- + * | Level: 2 (2 levels) | 46 | 42 | 38 | + * -------------------------------------------- + * | Level: 3 (1 level) | - | 53 | 51 | + * -------------------------------------------- + * + * We have a magic formula for the Magic_N below: + * + * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) + * + * where Number_of_levels = (4 - Level). We are only interested in the + * value for Entry_Level for the stage2 page table. + * + * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: + * + * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) + * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) + * + * Here is one way to explain the Magic Formula: + * + * x = log2(Size_of_Entry_Level_Table) + * + * Since, we can resolve (PAGE_SHIFT - 3) bits@each level, and another + * PAGE_SHIFT bits in the PTE, we have : + * + * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) + * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 + * where n = number of levels, and since each pointer is 8bytes, we have: + * + * x = Bits_Entry_Level + 3 + * = IPA_SHIFT - (PAGE_SHIFT - 3) * n + * + * The only constraint here is that, we have to find the number of page table + * levels for a given IPA size (which we do, see stage2_pt_levels()) + */ +#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) -#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) #define VTTBR_VMID_SHIFT (UL(48)) #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index 6b36fc3..4f22772 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -145,7 +145,6 @@ static inline unsigned long __kern_hyp_va(unsigned long v) #define kvm_phys_shift(kvm) KVM_PHYS_SHIFT #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) -#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK static inline bool kvm_page_empty(void *ptr) { @@ -501,5 +500,29 @@ static inline int hyp_map_aux_data(void) #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) +/* + * Get the magic number 'x' for VTTBR:BADDR of this KVM instance. + * With v8.2 LVA extensions, 'x' should be a minimum of 6 with + * 52bit IPS. + */ +static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels) +{ + int x = ARM64_VTTBR_X(ipa_shift, levels); + + return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x; +} + +static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels) +{ + unsigned int x = arm64_vttbr_x(ipa_shift, levels); + + return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x); +} + +static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) +{ + return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)); +} + #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ -- 2.7.4
next prev parent reply other threads:[~2018-07-18 9:18 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-07-18 9:18 [PATCH v4 00/20] kvm: arm64: Dynamic IPA and 52bit IPA Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 01/20] virtio: mmio-v1: Validate queue PFN Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-22 15:55 ` Michael S. Tsirkin 2018-07-22 15:55 ` Michael S. Tsirkin 2018-07-18 9:18 ` [PATCH v4 02/20] virtio: pci-legacy: Validate queue pfn Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-22 15:53 ` Michael S. Tsirkin 2018-07-22 15:53 ` Michael S. Tsirkin 2018-07-23 9:44 ` Suzuki K Poulose 2018-07-23 9:44 ` Suzuki K Poulose 2018-07-23 12:54 ` Marc Zyngier 2018-07-23 12:54 ` Marc Zyngier 2018-07-23 14:20 ` Michael S. Tsirkin 2018-07-23 14:20 ` Michael S. Tsirkin 2018-07-18 9:18 ` [PATCH v4 03/20] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 04/20] kvm: arm/arm64: Remove spurious WARN_ON Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 05/20] kvm: arm64: Add helper for loading the stage2 setting for a VM Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-08-30 9:39 ` Christoffer Dall 2018-08-30 9:39 ` Christoffer Dall 2018-09-03 10:03 ` Suzuki K Poulose 2018-09-03 10:03 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 06/20] arm64: Add a helper for PARange to physical shift conversion Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-08-30 9:42 ` Christoffer Dall 2018-08-30 9:42 ` Christoffer Dall 2018-09-03 10:06 ` Suzuki K Poulose 2018-09-03 10:06 ` Suzuki K Poulose 2018-09-03 11:13 ` Christoffer Dall 2018-09-03 11:13 ` Christoffer Dall 2018-07-18 9:18 ` [PATCH v4 07/20] kvm: arm64: Clean up VTCR_EL2 initialisation Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 08/20] kvm: arm64: Configure VTCR_EL2 per VM Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-08-30 10:02 ` Christoffer Dall 2018-08-30 10:02 ` Christoffer Dall 2018-07-18 9:18 ` [PATCH v4 09/20] kvm: arm/arm64: Prepare for VM specific stage2 translations Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 10/20] kvm: arm64: Prepare for dynamic stage2 page table layout Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 11/20] kvm: arm64: Make stage2 page table layout dynamic Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose [this message] 2018-07-18 9:18 ` [PATCH v4 12/20] kvm: arm64: Dynamic configuration of VTTBR mask Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 13/20] kvm: arm64: Configure VTCR_EL2.SL0 per VM Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 14/20] kvm: arm64: Switch to per VM IPA limit Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 15/20] vgic: Add support for 52bit guest physical address Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:18 ` [PATCH v4 16/20] kvm: arm64: Add 52bit support for PAR to HPFAR conversoin Suzuki K Poulose 2018-07-18 9:18 ` Suzuki K Poulose 2018-07-18 9:19 ` [PATCH v4 17/20] kvm: arm64: Set a limit on the IPA size Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-07-18 9:19 ` [PATCH v4 18/20] kvm: arm64: Limit the minimum number of page table levels Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-07-18 9:19 ` [PATCH v4 19/20] kvm: arm/arm64: Expose supported physical address limit for VM Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-07-18 9:19 ` [PATCH v4 20/20] kvm: arm64: Allow tuning the physical address size " Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-08-30 12:40 ` Christoffer Dall 2018-08-30 12:40 ` Christoffer Dall 2018-09-03 10:14 ` Suzuki K Poulose 2018-09-03 10:14 ` Suzuki K Poulose 2018-07-18 9:19 ` [kvmtool PATCH v4 21/24] kvmtool: Allow backends to run checks on the KVM device fd Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-07-18 9:19 ` [kvmtool PATCH v4 22/24] kvmtool: arm64: Add support for guest physical address size Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-07-18 9:19 ` [kvmtool PATCH v4 23/24] kvmtool: arm64: Switch memory layout Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose 2018-07-18 9:19 ` [kvmtool PATCH v4 24/24] kvmtool: arm: Add support for creating VM with PA size Suzuki K Poulose 2018-07-18 9:19 ` Suzuki K Poulose
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