From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2
Date: Mon, 22 Oct 2018 14:57:23 +0200 [thread overview]
Message-ID: <1540213077-15211-1-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
From: Aleksandar Markovic <amarkovic@wavecomp.com>
The following changes since commit b312532fd03413d0e6ae6767ec793a3e30f487b8:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2018-10-19 19:01:07 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-oct-2018-part-2
for you to fetch changes up to 2ec219776c633df9e43c5fa1557f70ee4f735f9d:
target/mips: Fix decoding of ALIGN and DALIGN instructions (2018-10-22 14:41:47 +0200)
----------------------------------------------------------------
MIPS queue for October 2018 - part 2
Limited support for R5900 ISA, MMI ASE, and two misc fixes.
----------------------------------------------------------------
Aleksandar Markovic (2):
target/mips: Fix the title of translate.c
target/mips: Fix decoding of ALIGN and DALIGN instructions
Fredrik Noring (32):
target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor
constants
disas/mips: Define R5900 disassembly constants
target/mips: R5900 Multimedia Instruction overview note
target/mips: Define R5900 MMI class, and LQ and SQ opcode constants
target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode
constants
target/mips: Define R5900 MMI0 opcode constants
target/mips: Define R5900 MMI1 opcode constants
target/mips: Define R5900 MMI2 opcode constants
target/mips: Define R5900 MMI3 opcode constants
target/mips: Placeholder for R5900 SQ, handle user mode RDHWR
target/mips: Placeholder for R5900 LQ
target/mips: Placeholder for R5900 MMI instruction class
target/mips: Placeholder for R5900 MMI0 instruction subclass
target/mips: Placeholder for R5900 MMI1 instruction subclass
target/mips: Placeholder for R5900 MMI2 instruction subclass
target/mips: Placeholder for R5900 MMI3 instruction subclass
target/mips: Support R5900 three-operand MULT and MULTU instructions
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
target/mips: Support R5900 DIV1 and DIVU1 instructions
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS
IV
target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only
tests/tcg/mips: Test R5900 three-operand MULT
tests/tcg/mips: Test R5900 three-operand MULTU
tests/tcg/mips: Test R5900 three-operand MULT1
tests/tcg/mips: Test R5900 three-operand MULTU1
tests/tcg/mips: Test R5900 MFLO1 and MFHI1
tests/tcg/mips: Test R5900 MTLO1 and MTHI1
tests/tcg/mips: Test R5900 DIV1
tests/tcg/mips: Test R5900 DIVU1
target/mips: Define the R5900 CPU
linux-user/mips: Recognise the R5900 CPU model
disas/mips.c | 16 +
linux-user/mips/target_elf.h | 3 +
target/mips/mips-defs.h | 3 +
target/mips/translate.c | 865 ++++++++++++++++++++++++++++++++++++-
target/mips/translate_init.inc.c | 59 +++
tests/tcg/mips/mipsr5900/Makefile | 30 ++
tests/tcg/mips/mipsr5900/div1.c | 73 ++++
tests/tcg/mips/mipsr5900/divu1.c | 48 ++
tests/tcg/mips/mipsr5900/mflohi1.c | 35 ++
tests/tcg/mips/mipsr5900/mtlohi1.c | 40 ++
tests/tcg/mips/mipsr5900/mult.c | 76 ++++
tests/tcg/mips/mipsr5900/multu.c | 68 +++
12 files changed, 1297 insertions(+), 19 deletions(-)
create mode 100644 tests/tcg/mips/mipsr5900/Makefile
create mode 100644 tests/tcg/mips/mipsr5900/div1.c
create mode 100644 tests/tcg/mips/mipsr5900/divu1.c
create mode 100644 tests/tcg/mips/mipsr5900/mflohi1.c
create mode 100644 tests/tcg/mips/mipsr5900/mtlohi1.c
create mode 100644 tests/tcg/mips/mipsr5900/mult.c
create mode 100644 tests/tcg/mips/mipsr5900/multu.c
--
2.7.4
next reply other threads:[~2018-10-22 12:58 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-22 12:57 Aleksandar Markovic [this message]
2018-10-22 12:57 ` [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 02/34] disas/mips: Define R5900 disassembly constants Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 03/34] target/mips: R5900 Multimedia Instruction overview note Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 07/34] target/mips: Define R5900 MMI1 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 08/34] target/mips: Define R5900 MMI2 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 09/34] target/mips: Define R5900 MMI3 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 14/34] target/mips: Placeholder for R5900 MMI1 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 24/34] tests/tcg/mips: Test R5900 three-operand MULTU Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 26/34] tests/tcg/mips: Test R5900 three-operand MULTU1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 29/34] tests/tcg/mips: Test R5900 DIV1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 30/34] tests/tcg/mips: Test R5900 DIVU1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions Aleksandar Markovic
2018-10-23 19:49 ` [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2 Peter Maydell
2018-10-23 20:37 ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
2018-10-24 8:04 ` Richard Henderson
2018-10-25 17:01 ` Fredrik Noring
2018-10-25 18:03 ` Maciej W. Rozycki
2018-10-25 18:20 ` Fredrik Noring
2018-10-26 7:26 ` Richard Henderson
2018-10-26 13:12 ` Maciej W. Rozycki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1540213077-15211-1-git-send-email-aleksandar.markovic@rt-rk.com \
--to=aleksandar.markovic@rt-rk.com \
--cc=amarkovic@wavecomp.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.